Static Timing Analysis

Project : Slave
Build Time : 06/06/19 09:01:24
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 58.569 MHz
UART_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 51.709 MHz
Clock_1 CyMASTER_CLK 12.000 kHz 12.000 kHz 85.668 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 83333.3ns(12 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 85.668 MHz 11.673 83321.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 2.628
macrocell9 U(0,2) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.905
statusicell3 U(0,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 86.386 MHz 11.576 83321.757
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 3.571
macrocell9 U(0,2) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.905
statusicell3 U(0,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 91.149 MHz 10.971 83322.362
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.621
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 91.886 MHz 10.883 83322.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.573
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_25/main_1 108.096 MHz 9.251 83324.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_25/main_1 3.231
macrocell29 U(0,1) 1 Net_25 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 120.062 MHz 8.329 83325.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.309
macrocell27 U(1,2) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 120.062 MHz 8.329 83325.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.309
macrocell28 U(1,2) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_25/main_0 135.355 MHz 7.388 83325.945
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_25/main_0 2.628
macrocell29 U(0,1) 1 Net_25 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 141.784 MHz 7.053 83326.280
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 1.210
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.333
macrocell26 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 141.844 MHz 7.050 83326.283
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(1,2) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.290
macrocell28 U(1,2) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 58.569 MHz 17.074 24.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.954
macrocell6 U(0,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 87.161 MHz 11.473 30.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 5.954
macrocell22 U(0,1) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 87.161 MHz 11.473 30.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 5.954
macrocell23 U(0,1) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 94.047 MHz 10.633 31.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.114
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 94.047 MHz 10.633 31.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 5.114
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 94.073 MHz 10.630 31.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.111
macrocell24 U(0,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 94.073 MHz 10.630 31.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.111
macrocell25 U(0,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 51.709 MHz 19.339 13022.328
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 7.063
macrocell5 U(0,2) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,2) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 53.752 MHz 18.604 13023.063
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 6.328
macrocell5 U(0,2) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,2) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 55.084 MHz 18.154 13023.513
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.499
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.865
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.964 MHz 17.252 13024.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 3.597
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.865
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 60.183 MHz 16.616 13025.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 4.340
macrocell5 U(0,2) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,2) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.857 MHz 16.432 13025.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 2.777
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.865
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.793 MHz 16.183 13025.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 3.588
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.865
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 63.902 MHz 15.649 13026.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.323
macrocell7 U(0,1) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 5.896
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 64.708 MHz 15.454 13026.213
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,2) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 3.178
macrocell5 U(0,2) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,2) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxSts\/status_4 66.751 MHz 14.981 13026.686
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,0) 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/clock_0 \UART:BUART:rx_load_fifo\/q 1.250
Route 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/q \UART:BUART:rx_status_4\/main_0 3.985
macrocell7 U(0,1) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_0 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 5.896
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(1,2) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.896
statusicell3 U(0,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.693
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.333
macrocell26 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 3.089
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.309
macrocell27 U(1,2) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 3.089
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.309
macrocell28 U(1,2) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(1,2) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.290
macrocell28 U(1,2) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_25/main_0 3.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_25/main_0 2.628
macrocell29 U(0,1) 1 Net_25 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_25/main_1 4.011
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_25/main_1 3.231
macrocell29 U(0,1) 1 Net_25 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.810
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.621
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 4.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.573
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 8.693
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.810
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 2.628
macrocell9 U(0,2) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.905
statusicell3 U(0,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 7.120
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.111
macrocell24 U(0,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 7.120
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.111
macrocell25 U(0,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 7.123
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.114
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 7.123
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 5.114
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 7.963
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 5.954
macrocell22 U(0,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 7.963
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 5.954
macrocell23 U(0,1) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 13.604
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_18 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.954
macrocell6 U(0,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.252
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.540
macrocell13 U(1,0) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_2\/main_2 2.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_2\/main_2 2.678
macrocell13 U(1,0) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_0\/main_2 2.897
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_0\/main_2 2.707
macrocell12 U(1,0) 1 \UART:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.308
macrocell20 U(0,2) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.310
macrocell20 U(0,2) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART:BUART:rx_count_0\ \UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.312
macrocell20 U(0,2) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 3.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,0) 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/clock_0 \UART:BUART:rx_last\/q 1.250
Route 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 2.234
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell10 U(1,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.295
macrocell10 U(1,1) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:tx_state_2\/main_3 3.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
macrocell13 U(1,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:tx_state_2\/main_3 2.518
macrocell13 U(1,0) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_25/q Pin_1(0)_PAD 24.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(0,1) 1 Net_25 Net_25/clock_0 Net_25/q 1.250
Route 1 Net_25 Net_25/q Pin_1(0)/pin_input 7.485
iocell5 P2[1] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.891
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 30.451
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_13/main_0 2.295
macrocell1 U(1,1) 1 Net_13 Net_13/main_0 Net_13/q 3.350
Route 1 Net_13 Net_13/q Tx_1(0)/pin_input 6.589
iocell4 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000