Define the registers addresses and the positions and masks of the variables from the registers.
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#define | TLE493D_AW2B6_REGS_COUNT (0x16U + 1U) |
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#define | TLE493D_AW2B6_Bx_REG (0x00U) |
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#define | TLE493D_AW2B6_By_REG (0x01U) |
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#define | TLE493D_AW2B6_Bz_REG (0x02U) |
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#define | TLE493D_AW2B6_Temp_REG (0x03U) |
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#define | TLE493D_AW2B6_Bx2_REG (0x04U) |
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#define | TLE493D_AW2B6_Temp2_REG (0x05U) |
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#define | TLE493D_AW2B6_Diag_REG (0x06U) |
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#define | TLE493D_AW2B6_Diag_P_MSK (1U << 7) |
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#define | TLE493D_AW2B6_Diag_P_POS (7U) |
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#define | TLE493D_AW2B6_Diag_FF_MSK (1U << 6) |
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#define | TLE493D_AW2B6_Diag_FF_POS (6U) |
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#define | TLE493D_AW2B6_Diag_CF_MSK (1U << 5) |
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#define | TLE493D_AW2B6_Diag_CF_POS (5U) |
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#define | TLE493D_AW2B6_Diag_T_MSK (1U << 4) |
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#define | TLE493D_AW2B6_Diag_T_POS (4U) |
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#define | TLE493D_AW2B6_Diag_PD3_MSK (1U << 3) |
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#define | TLE493D_AW2B6_Diag_PD3_POS (3U) |
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#define | TLE493D_AW2B6_Diag_PD0_MSK (1U << 2) |
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#define | TLE493D_AW2B6_Diag_PD0_POS (2U) |
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#define | TLE493D_AW2B6_Diag_FRM_MSK (3U << 0) |
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#define | TLE493D_AW2B6_Diag_FRM_POS (0U) |
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#define | TLE493D_AW2B6_XL_REG (0x07U) |
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#define | TLE493D_AW2B6_XH_REG (0x08U) |
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#define | TLE493D_AW2B6_YL_REG (0x09U) |
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#define | TLE493D_AW2B6_YH_REG (0x0AU) |
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#define | TLE493D_AW2B6_ZL_REG (0x0BU) |
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#define | TLE493D_AW2B6_ZH_REG (0x0CU) |
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#define | TLE493D_AW2B6_WU_REG (0x0DU) |
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#define | TLE493D_AW2B6_WU_WA_POS (0x7U) |
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#define | TLE493D_AW2B6_WU_WA_MSK (0x1U << 7) |
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#define | TLE493D_AW2B6_WU_WU_POS (0x6U) |
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#define | TLE493D_AW2B6_WU_WU_ENABLE (0x1U << 6) |
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#define | TLE493D_AW2B6_WU_WU_DISABLE (0x0U << 6) |
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#define | TLE493D_AW2B6_WU_WU_MSK (0x1U << 6) |
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#define | TLE493D_AW2B6_WU_XH_POS (0x3U) |
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#define | TLE493D_AW2B6_WU_XH_MSK (0x7U << 3) |
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#define | TLE493D_AW2B6_WU_XL_POS (0x3U) |
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#define | TLE493D_AW2B6_WU_XL_MSK (0x7U << 0) |
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#define | TLE493D_AW2B6_TMode_REG (0x0EU) |
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#define | TLE493D_AW2B6_TMode_TST_POS (6U) |
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#define | TLE493D_AW2B6_TMode_TST_MSK (3U << 6) |
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#define | TLE493D_AW2B6_TMode_TST_NORMAL (0U << 6) |
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#define | TLE493D_AW2B6_TMode_TST_Vhall (1U << 6) |
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#define | TLE493D_AW2B6_TMode_TST_Spintest (2U << 6) |
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#define | TLE493D_AW2B6_TMode_TST_SAT (3U << 6) |
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#define | TLE493D_AW2B6_TMode_YH_POS (3U) |
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#define | TLE493D_AW2B6_TMode_YH_MSK (7U << 3) |
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#define | TLE493D_AW2B6_TMode_YL_POS (0U) |
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#define | TLE493D_AW2B6_TMode_YL_MSK (7U << 0) |
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#define | TLE493D_AW2B6_TPhase_REG (0x0FU) |
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#define | TLE493D_AW2B6_TPhase_PH_POS (6U) |
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#define | TLE493D_AW2B6_TPhase_PH_MSK (3U << 6) |
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#define | TLE493D_AW2B6_TPhase_ZH_POS (3U) |
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#define | TLE493D_AW2B6_TPhase_ZH_MSK (7U << 3) |
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#define | TLE493D_AW2B6_TPhase_ZL_POS (0U) |
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#define | TLE493D_AW2B6_TPhase_ZL_MSK (7U << 0) |
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#define | TLE493D_AW2B6_Config_REG (0x10U) |
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#define | TLE493D_AW2B6_Config_DT_POS (0x7U) |
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#define | TLE493D_AW2B6_Config_DT_MSK (0x1U << 7) |
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#define | TLE493D_AW2B6_Config_DT_ENABLE (0x0U << 7) |
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#define | TLE493D_AW2B6_Config_DT_DISABLE (0x1U << 7) |
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#define | TLE493D_AW2B6_Config_AM_POS (0x6U) |
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#define | TLE493D_AW2B6_Config_AM_MSK (0x1U << 6) |
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#define | TLE493D_AW2B6_Config_AM_ENABLE_BZ_MEASURE (0x0U << 6) |
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#define | TLE493D_AW2B6_Config_AM_DISABLE_BZ_MEASURE (0x1U << 6) |
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#define | TLE493D_AW2B6_Config_TRIG_POS (0x4U) |
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#define | TLE493D_AW2B6_Config_TRIG_MSK (0x30U) |
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#define | TLE493D_AW2B6_Config_X2_POS (0x3U) |
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#define | TLE493D_AW2B6_Config_X2_MSK (1U << 3) |
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#define | TLE493D_AW2B6_Config_X2_DOUBLE (1U << 3) |
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#define | TLE493D_AW2B6_Config_X2_SIMPLE (0U << 3) |
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#define | TLE493D_AW2B6_Config_TL_mag_POS (0x1U) |
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#define | TLE493D_AW2B6_Config_TL_mag_MSK (3U << 1) |
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#define | TLE493D_AW2B6_Config_CP_POS (0x0U) |
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#define | TLE493D_AW2B6_Config_CP_MSK (0x1U) |
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#define | TLE493D_AW2B6_MOD1_REG (0x11U) |
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#define | TLE493D_AW2B6_MOD1_FP_POS (0x7U) |
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#define | TLE493D_AW2B6_MOD1_FP_MSK (1 << 0x7U) |
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#define | TLE493D_AW2B6_MOD1_IICadr_POS (0x5U) |
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#define | TLE493D_AW2B6_MOD1_IICadr_MSK (0x3U << 0x5U) |
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#define | TLE493D_AW2B6_MOD1_IICadr_A0 (0x0U << 0x5U) |
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#define | TLE493D_AW2B6_MOD1_IICadr_A1 (0x1U << 0x5U) |
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#define | TLE493D_AW2B6_MOD1_IICadr_A2 (0x2U << 0x5U) |
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#define | TLE493D_AW2B6_MOD1_IICadr_A3 (0x3U << 0x5U) |
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#define | TLE493D_AW2B6_MOD1_PR_POS (0x4U) |
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#define | TLE493D_AW2B6_MOD1_PR_MSK (0x1U << 0x4U) |
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#define | TLE493D_AW2B6_MOD1_PR_2BYTE (0x0U << 0x4U) |
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#define | TLE493D_AW2B6_MOD1_PR_1BYTE (0x1U << 0x4U) |
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#define | TLE493D_AW2B6_MOD1_CA_POS (0x3U) |
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#define | TLE493D_AW2B6_MOD1_CA_MSK (1 << 0x3U) |
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#define | TLE493D_AW2B6_MOD1_CA_ENABLE (0U << 0x3U) |
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#define | TLE493D_AW2B6_MOD1_CA_DISABLE (1U << 0x3U) |
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#define | TLE493D_AW2B6_MOD1_INT_POS (0x2U) |
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#define | TLE493D_AW2B6_MOD1_INT_MSK (0x1U << 0x2U) |
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#define | TLE493D_AW2B6_MOD1_INT_ENABLE (0x0U << 0x2U) |
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#define | TLE493D_AW2B6_MOD1_INT_DISABLE (0x1U << 0x2U) |
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#define | TLE493D_AW2B6_MOD1_MODE_POS (0x0U) |
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#define | TLE493D_AW2B6_MOD1_MODE_MSK (0x3U) |
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#define | TLE493D_AW2B6_MOD1_MODE_LOW_POWER (0U) |
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#define | TLE493D_AW2B6_MOD1_MODE_MCM (0x1U) |
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#define | TLE493D_AW2B6_MOD1_MODE_FAST_MODE (0x3U) |
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#define | TLE493D_AW2B6_Reserved_REG (0x12U) |
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#define | TLE493D_AW2B6_MOD2_REG (0x13U) |
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#define | TLE493D_AW2B6_MOD2_PRD_POS (0x5U) |
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#define | TLE493D_AW2B6_MOD2_PRD_MSK (0x7U << 5) |
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#define | TLE493D_AW2B6_Reserved2_REG (0x14U) |
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#define | TLE493D_AW2B6_Reserved3_REG (0x15U) |
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#define | TLE493D_AW2B6_Ver_REG (0x16U) |
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#define | TLE493D_AW2B6_Ver_HWV_POS (0x00U) |
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#define | TLE493D_AW2B6_Ver_HWV_MSK (0x0FU) |
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#define | TLE493D_AW2B6_Ver_HWV_B21 (0x09U) |
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#define | TLE493D_AW2B6_Ver_TYPE_POS (0x4U) |
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#define | TLE493D_AW2B6_Ver_TYPE_MSK (0x3U << 4) |
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Define the registers addresses and the positions and masks of the variables from the registers.
Defines:
*_REG register positions
*_POS Position of value in register (starting from MSB)
*_MSK Mask for a value in register