Define the registers addresses and the positions and masks of the variables from the registers.
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#define | TLV493D_A1B6_I2C_RESET_ADDR (0x00U) |
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#define | TLV493D_A1B6_I2C_RECOV_ADDR (0xFFU) |
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#define | TLV493D_A1B6_I2C_DEFAULT_ADDR_HIGH (0xBCU) |
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#define | TLV493D_A1B6_I2C_DEFAULT_ADDR_LOW (0x3EU) |
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#define | TLV493D_A1B6_READ_REGS_COUNT (0x0AU) |
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#define | TLV493D_A1B6_Bx_REG (0x0U) |
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#define | TLV493D_A1B6_By_REG (0x1U) |
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#define | TLV493D_A1B6_Bz_REG (0x2U) |
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#define | TLV493D_A1B6_Temp_REG (0x3U) |
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#define | TLV493D_A1B6_Temp_Temp_POS (0x4U) |
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#define | TLV493D_A1B6_Temp_Temp_MSK (0xFU << 4) |
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#define | TLV493D_A1B6_Temp_FRM_POS (0x2U) |
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#define | TLV493D_A1B6_Temp_FRM_MSK (0x3U << 2) |
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#define | TLV493D_A1B6_Temp_CH_POS (0x0U) |
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#define | TLV493D_A1B6_Temp_CH_MSK (0x3U) |
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#define | TLV493D_A1B6_Bx2_REG (0x4U) |
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#define | TLV493D_A1B6_Bx2_Bx_POS (0x4U) |
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#define | TLV493D_A1B6_Bx2_Bx_MSK (0xFU << 4) |
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#define | TLV493D_A1B6_Bx2_By_POS (0x0U) |
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#define | TLV493D_A1B6_Bx2_By_MSK (0xFU) |
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#define | TLV493D_A1B6_Bz2_REG (0x5U) |
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#define | TLV493D_A1B6_Bz2_Reserved_POS (0x7U) |
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#define | TLV493D_A1B6_Bz2_Reserved_MSK (0x1U << 7) |
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#define | TLV493D_A1B6_Bz2_T_POS (0x6U) |
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#define | TLV493D_A1B6_Bz2_T_MSK (0x1U << 6) |
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#define | TLV493D_A1B6_Bz2_F_POS (0x5U) |
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#define | TLV493D_A1B6_Bz2_F_MSK (0x1U << 5) |
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#define | TLV493D_A1B6_Bz2_PD_POS (0x4U) |
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#define | TLV493D_A1B6_Bz2_PD_MSK (0x1U << 4) |
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#define | TLV493D_A1B6_Bz2_Bz_POS (0x0U) |
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#define | TLV493D_A1B6_Bz2_Bz_MSK (0xFU) |
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#define | TLV493D_A1B6_Temp2_REG (0x6U) |
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#define | TLV493D_A1B6_Temp2_Temp_POS (0x0U) |
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#define | TLV493D_A1B6_Temp2_Temp_MSK (0xFF) |
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#define | TLV493D_A1B6_FactSet1_REG (0x7U) |
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#define | TLV493D_A1B6_FaceSet1_Reserved_POS (0x0U) |
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#define | TLV493D_A1B6_FaceSet1_Reserved_MSK (0xFF) |
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#define | TLV493D_A1B6_FactSet2_REG (0x8U) |
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#define | TLV493D_A1B6_FaceSet2_Reserved_POS (0x0U) |
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#define | TLV493D_A1B6_FaceSet2_Reserved_MSK (0xFF) |
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#define | TLV493D_A1B6_FactSet3_REG (0x9U) |
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#define | TLV493D_A1B6_FaceSet3_Reserved_POS (0x0U) |
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#define | TLV493D_A1B6_FaceSet3_Reserved_MSK (0xFF) |
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#define | TLV493D_A1B6_WRITE_REGS_COUNT (0x04U) |
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#define | TLV493D_A1B6_Res_REG (0x0U) |
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#define | TLV493D_A1B6_Res_Reserved_POS (0x0U) |
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#define | TLV493D_A1B6_Res_Reserved_MSK (0xFF) |
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#define | TLV493D_A1B6_MOD1_REG (0x1U) |
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#define | TLV493D_A1B6_MOD1_P_POS (0x7U) |
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#define | TLV493D_A1B6_MOD1_P_MSK (0x1U << 7) |
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#define | TLV493D_A1B6_MOD1_IICAddr_POS (0x5U) |
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#define | TLV493D_A1B6_MOD1_IICAddr_MSK (0x3U << 5) |
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#define | TLV493D_A1B6_MOD1_IICAddr_16_94 (0x3U << 5) |
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#define | TLV493D_A1B6_MOD1_IICAddr_1E_9C (0x2U << 5) |
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#define | TLV493D_A1B6_MOD1_IICAddr_36_B4 (0x1U << 5) |
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#define | TLV493D_A1B6_MOD1_IICAddr_3E_BC (0x0U << 5) |
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#define | TLV493D_A1B6_MOD1_Reserved_POS (0x3U) |
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#define | TLV493D_A1B6_MOD1_Reserved_MSK (0x3U << 3) |
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#define | TLV493D_A1B6_MOD1_INT_POS (0x2U) |
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#define | TLV493D_A1B6_MOD1_INT_MSK (0x1U << 2) |
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#define | TLV493D_A1B6_MOD1_INT_ENABLE (0x1U << 2) |
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#define | TLV493D_A1B6_MOD1_INT_DISABLE (0x0U << 2) |
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#define | TLV493D_A1B6_MOD1_FAST_POS (0x1U) |
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#define | TLV493D_A1B6_MOD1_FAST_MSK (0x1U << 1) |
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#define | TLV493D_A1B6_MOD1_FAST_ENABLE (0x1U << 1) |
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#define | TLV493D_A1B6_MOD1_FAST_DISABLE (0x0U << 1) |
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#define | TLV493D_A1B6_MOD1_LOW_POS (0x0U) |
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#define | TLV493D_A1B6_MOD1_LOW_MSK (0x1U) |
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#define | TLV493D_A1B6_MOD1_LOW_ENABLE (0x1U) |
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#define | TLV493D_A1B6_MOD1_LOW_DISABLE (0x0U) |
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#define | TLV493D_A1B6_Res2_REG (0x2U) |
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#define | TLV493D_A1B6_Res2_Reserved_POS (0x0U) |
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#define | TLV493D_A1B6_Res2_Reserved_MSK (0xFF) |
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#define | TLV493D_A1B6_MOD2_REG (0x3U) |
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#define | TLV493D_A1B6_MOD2_T_POS (0x7U) |
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#define | TLV493D_A1B6_MOD2_T_MSK (0x1U << 7) |
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#define | TLV493D_A1B6_MOD2_T_DISABLE (0x1U << 7) |
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#define | TLV493D_A1B6_MOD2_T_ENABLE (0x0U << 7) |
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#define | TLV493D_A1B6_MOD2_LP_POS (0x6U) |
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#define | TLV493D_A1B6_MOD2_LP_MSK (0x1U << 6) |
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#define | TLV493D_A1B6_MOD2_LP_ULTRA_LOW_POWER (0x0U << 6) |
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#define | TLV493D_A1B6_MOD2_LP_LOW_POWER (0x1U << 6) |
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#define | TLV493D_A1B6_MOD2_PT_POS (0x5U) |
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#define | TLV493D_A1B6_MOD2_PT_MSK (0x1U << 5) |
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#define | TLV493D_A1B6_MOD2_PT_DISABLE (0x0U << 5) |
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#define | TLV493D_A1B6_MOD2_PT_ENABLE (0x1U << 5) |
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#define | TLV493D_A1B6_MOD2_Reserved_POS (0x0U) |
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#define | TLV493D_A1B6_MOD2_Reserved_MSK (0x1FU) |
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Define the registers addresses and the positions and masks of the variables from the registers.
Defines:
*_REG register positions
*_POS Position of value in register (starting from MSB)
*_MSK Mask for a value in register