28 #ifndef SRC_TLX493D_AW2B6_DEFINES_H_ 29 #define SRC_TLX493D_AW2B6_DEFINES_H_ 34 #define TLE493D_AW2B6_REGS_COUNT (0x16U + 1U) 36 #define TLE493D_AW2B6_Bx_REG (0x00U) 38 #define TLE493D_AW2B6_By_REG (0x01U) 40 #define TLE493D_AW2B6_Bz_REG (0x02U) 42 #define TLE493D_AW2B6_Temp_REG (0x03U) 44 #define TLE493D_AW2B6_Bx2_REG (0x04U) 46 #define TLE493D_AW2B6_Temp2_REG (0x05U) 48 #define TLE493D_AW2B6_Diag_REG (0x06U) 49 #define TLE493D_AW2B6_Diag_P_MSK (1U << 7) 50 #define TLE493D_AW2B6_Diag_P_POS (7U) 51 #define TLE493D_AW2B6_Diag_FF_MSK (1U << 6) 52 #define TLE493D_AW2B6_Diag_FF_POS (6U) 53 #define TLE493D_AW2B6_Diag_CF_MSK (1U << 5) 54 #define TLE493D_AW2B6_Diag_CF_POS (5U) 55 #define TLE493D_AW2B6_Diag_T_MSK (1U << 4) 56 #define TLE493D_AW2B6_Diag_T_POS (4U) 57 #define TLE493D_AW2B6_Diag_PD3_MSK (1U << 3) 58 #define TLE493D_AW2B6_Diag_PD3_POS (3U) 59 #define TLE493D_AW2B6_Diag_PD0_MSK (1U << 2) 60 #define TLE493D_AW2B6_Diag_PD0_POS (2U) 61 #define TLE493D_AW2B6_Diag_FRM_MSK (3U << 0) 62 #define TLE493D_AW2B6_Diag_FRM_POS (0U) 64 #define TLE493D_AW2B6_XL_REG (0x07U) 66 #define TLE493D_AW2B6_XH_REG (0x08U) 68 #define TLE493D_AW2B6_YL_REG (0x09U) 70 #define TLE493D_AW2B6_YH_REG (0x0AU) 72 #define TLE493D_AW2B6_ZL_REG (0x0BU) 74 #define TLE493D_AW2B6_ZH_REG (0x0CU) 76 #define TLE493D_AW2B6_WU_REG (0x0DU) 77 #define TLE493D_AW2B6_WU_WA_POS (0x7U) 78 #define TLE493D_AW2B6_WU_WA_MSK (0x1U << 7) 79 #define TLE493D_AW2B6_WU_WU_POS (0x6U) 80 #define TLE493D_AW2B6_WU_WU_ENABLE (0x1U << 6) 81 #define TLE493D_AW2B6_WU_WU_DISABLE (0x0U << 6) 82 #define TLE493D_AW2B6_WU_WU_MSK (0x1U << 6) 83 #define TLE493D_AW2B6_WU_XH_POS (0x3U) 84 #define TLE493D_AW2B6_WU_XH_MSK (0x7U << 3) 85 #define TLE493D_AW2B6_WU_XL_POS (0x3U) 86 #define TLE493D_AW2B6_WU_XL_MSK (0x7U << 0) 89 #define TLE493D_AW2B6_TMode_REG (0x0EU) 90 #define TLE493D_AW2B6_TMode_TST_POS (6U) 91 #define TLE493D_AW2B6_TMode_TST_MSK (3U << 6) 92 #define TLE493D_AW2B6_TMode_TST_NORMAL (0U << 6) 93 #define TLE493D_AW2B6_TMode_TST_Vhall (1U << 6) 94 #define TLE493D_AW2B6_TMode_TST_Spintest (2U << 6) 95 #define TLE493D_AW2B6_TMode_TST_SAT (3U << 6) 96 #define TLE493D_AW2B6_TMode_YH_POS (3U) 97 #define TLE493D_AW2B6_TMode_YH_MSK (7U << 3) 98 #define TLE493D_AW2B6_TMode_YL_POS (0U) 99 #define TLE493D_AW2B6_TMode_YL_MSK (7U << 0) 102 #define TLE493D_AW2B6_TPhase_REG (0x0FU) 103 #define TLE493D_AW2B6_TPhase_PH_POS (6U) 104 #define TLE493D_AW2B6_TPhase_PH_MSK (3U << 6) 105 #define TLE493D_AW2B6_TPhase_ZH_POS (3U) 106 #define TLE493D_AW2B6_TPhase_ZH_MSK (7U << 3) 107 #define TLE493D_AW2B6_TPhase_ZL_POS (0U) 108 #define TLE493D_AW2B6_TPhase_ZL_MSK (7U << 0) 111 #define TLE493D_AW2B6_Config_REG (0x10U) 113 #define TLE493D_AW2B6_Config_DT_POS (0x7U) 114 #define TLE493D_AW2B6_Config_DT_MSK (0x1U << 7) 115 #define TLE493D_AW2B6_Config_DT_ENABLE (0x0U << 7) 116 #define TLE493D_AW2B6_Config_DT_DISABLE (0x1U << 7) 118 #define TLE493D_AW2B6_Config_AM_POS (0x6U) 119 #define TLE493D_AW2B6_Config_AM_MSK (0x1U << 6) 120 #define TLE493D_AW2B6_Config_AM_ENABLE_BZ_MEASURE (0x0U << 6) 121 #define TLE493D_AW2B6_Config_AM_DISABLE_BZ_MEASURE (0x1U << 6) 123 #define TLE493D_AW2B6_Config_TRIG_POS (0x4U) 124 #define TLE493D_AW2B6_Config_TRIG_MSK (0x30U) 128 TLE493D_AW2B6_Config_TRIG_NONE = (0x0U << 4),
130 TLE493D_AW2B6_Config_TRIG_R0 = (0x1U << 4),
131 TLE493D_AW2B6_Config_TRIG_R6 = (0x2U << 4)
135 #define TLE493D_AW2B6_Config_X2_POS (0x3U) 136 #define TLE493D_AW2B6_Config_X2_MSK (1U << 3) 137 #define TLE493D_AW2B6_Config_X2_DOUBLE (1U << 3) 138 #define TLE493D_AW2B6_Config_X2_SIMPLE (0U << 3) 140 #define TLE493D_AW2B6_Config_TL_mag_POS (0x1U) 141 #define TLE493D_AW2B6_Config_TL_mag_MSK (3U << 1) 145 TLE493D_AW2B6_Config_TL_mag_TC0 = (0U << 1),
146 TLE493D_AW2B6_Config_TL_mag_TC1 = (1U << 1),
147 TLE493D_AW2B6_Config_TL_mag_TC2 = (2U << 1),
148 TLE493D_AW2B6_Config_TL_mag_TC3 = (3U << 1)
153 #define TLE493D_AW2B6_Config_CP_POS (0x0U) 154 #define TLE493D_AW2B6_Config_CP_MSK (0x1U) 157 #define TLE493D_AW2B6_MOD1_REG (0x11U) 158 #define TLE493D_AW2B6_MOD1_FP_POS (0x7U) 159 #define TLE493D_AW2B6_MOD1_FP_MSK (1 << 0x7U) 161 #define TLE493D_AW2B6_MOD1_IICadr_POS (0x5U) 162 #define TLE493D_AW2B6_MOD1_IICadr_MSK (0x3U << 0x5U) 165 #define TLE493D_AW2B6_MOD1_IICadr_A0 (0x0U << 0x5U) 166 #define TLE493D_AW2B6_MOD1_IICadr_A1 (0x1U << 0x5U) 167 #define TLE493D_AW2B6_MOD1_IICadr_A2 (0x2U << 0x5U) 168 #define TLE493D_AW2B6_MOD1_IICadr_A3 (0x3U << 0x5U) 170 #define TLE493D_AW2B6_MOD1_PR_POS (0x4U) 171 #define TLE493D_AW2B6_MOD1_PR_MSK (0x1U << 0x4U) 172 #define TLE493D_AW2B6_MOD1_PR_2BYTE (0x0U << 0x4U) 173 #define TLE493D_AW2B6_MOD1_PR_1BYTE (0x1U << 0x4U) 175 #define TLE493D_AW2B6_MOD1_CA_POS (0x3U) 176 #define TLE493D_AW2B6_MOD1_CA_MSK (1 << 0x3U) 177 #define TLE493D_AW2B6_MOD1_CA_ENABLE (0U << 0x3U) 178 #define TLE493D_AW2B6_MOD1_CA_DISABLE (1U << 0x3U) 180 #define TLE493D_AW2B6_MOD1_INT_POS (0x2U) 181 #define TLE493D_AW2B6_MOD1_INT_MSK (0x1U << 0x2U) 182 #define TLE493D_AW2B6_MOD1_INT_ENABLE (0x0U << 0x2U) 183 #define TLE493D_AW2B6_MOD1_INT_DISABLE (0x1U << 0x2U) 185 #define TLE493D_AW2B6_MOD1_MODE_POS (0x0U) 186 #define TLE493D_AW2B6_MOD1_MODE_MSK (0x3U) 187 #define TLE493D_AW2B6_MOD1_MODE_LOW_POWER (0U) 188 #define TLE493D_AW2B6_MOD1_MODE_MCM (0x1U) 189 #define TLE493D_AW2B6_MOD1_MODE_FAST_MODE (0x3U) 193 TLE493D_AW2B6_I2C_NOTRIG = (0x00U << 5),
194 TLE493D_AW2B6_I2C_TRIG_AFTER_WRITE = (0x01U << 5),
195 TLE493D_AW2B6_I2C_TRIG_BEFORE_READ = (0x02U << 5),
196 TLE493D_AW2B6_I2C_TRIG_AFTER_READ_R06 = (0x04U << 5),
200 #define TLE493D_AW2B6_Reserved_REG (0x12U) 202 #define TLE493D_AW2B6_MOD2_REG (0x13U) 204 #define TLE493D_AW2B6_MOD2_PRD_POS (0x5U) 205 #define TLE493D_AW2B6_MOD2_PRD_MSK (0x7U << 5) 209 TLE493D_AW2B6_MOD2_PRD_770 = (0x0U << 5),
210 TLE493D_AW2B6_MOD2_PRD_97 = (0x1U << 5),
211 TLE493D_AW2B6_MOD2_PRD_24 = (0x2U << 5),
212 TLE493D_AW2B6_MOD2_PRD_12 = (0x3U << 5),
213 TLE493D_AW2B6_MOD2_PRD_6 = (0x4U << 5),
214 TLE493D_AW2B6_MOD2_PRD_3 = (0x5U << 5),
215 TLE493D_AW2B6_MOD2_PRD_04 = (0x6U << 5),
216 TLE493D_AW2B6_MOD2_PRD_005 = (0x7U << 5)
221 #define TLE493D_AW2B6_Reserved2_REG (0x14U) 223 #define TLE493D_AW2B6_Reserved3_REG (0x15U) 225 #define TLE493D_AW2B6_Ver_REG (0x16U) 227 #define TLE493D_AW2B6_Ver_HWV_POS (0x00U) 228 #define TLE493D_AW2B6_Ver_HWV_MSK (0x0FU) 229 #define TLE493D_AW2B6_Ver_HWV_B21 (0x09U) 231 #define TLE493D_AW2B6_Ver_TYPE_POS (0x4U) 232 #define TLE493D_AW2B6_Ver_TYPE_MSK (0x3U << 4) 239 TLE493D_AW2B6_I2C_A0_ADDR = 0x6AU,
240 TLE493D_AW2B6_I2C_A1_ADDR = 0x44U,
241 TLE493D_AW2B6_I2C_A2_ADDR = 0xF0U,
242 TLE493D_AW2B6_I2C_A3_ADDR = 0x88U
247 uint8_t Bx, By, Bz, Temp;
253 uint8_t WU, TMode, TPhase;
254 uint8_t Config, MOD1;
257 uint8_t Reserved2, Reserved3;
TLE493D_lp_update_freq_t
Low power mode update frequencies.
Definition: TLE_AW2B6_defines.h:208
TLE493D_address_t
Sensor bus addresses.
Definition: TLE_AW2B6_defines.h:238
TLE493D_i2c_trigger_mode_t
Trigger bits for I2C Write commands.
Definition: TLE_AW2B6_defines.h:192
TLE493D_magnetic_comp_t
Sensitivity for magnetic compensation.
Definition: TLE_AW2B6_defines.h:144
TLE493D_Config_trigger_mode_t
Register-configurable trigger modes.
Definition: TLE_AW2B6_defines.h:127
Internal registers of the TLE493D sensor family.
Definition: TLE_AW2B6_defines.h:246