Static Timing Analysis

Project : CyController1
Build Time : 10/12/15 13:16:47
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_IntClock(routed) ADC_IntClock(routed) 1.263 MHz 1.263 MHz N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 84.027 MHz
ADC_IntClock CyMASTER_CLK 1.263 MHz 1.263 MHz 29.398 MHz
Clock_1 CyMASTER_CLK 366.211  Hz 366.211  Hz 84.027 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 791.667ns(1.26316 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_one_hot_13\/main_0 29.398 MHz 34.016 757.651
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 8.064
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_13\/main_0 10.826
macrocell23 U(2,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_13\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_one_hot_20\/main_0 29.398 MHz 34.016 757.651
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 8.064
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_20\/main_0 10.826
macrocell30 U(2,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_20\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_one_hot_22\/main_0 29.398 MHz 34.016 757.651
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 8.064
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_22\/main_0 10.826
macrocell32 U(2,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_22\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_2\/q \ADC:AMuxHw_2_Decoder_one_hot_13\/main_0 29.576 MHz 33.811 757.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_2\ \ADC:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_2\ \ADC:AMuxHw_2_Decoder_old_id_2\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_6 7.859
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_13\/main_0 10.826
macrocell23 U(2,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_13\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_2\/q \ADC:AMuxHw_2_Decoder_one_hot_20\/main_0 29.576 MHz 33.811 757.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_2\ \ADC:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_2\ \ADC:AMuxHw_2_Decoder_old_id_2\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_6 7.859
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_20\/main_0 10.826
macrocell30 U(2,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_20\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_2\/q \ADC:AMuxHw_2_Decoder_one_hot_22\/main_0 29.576 MHz 33.811 757.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_2\ \ADC:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_2\ \ADC:AMuxHw_2_Decoder_old_id_2\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_6 7.859
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_22\/main_0 10.826
macrocell32 U(2,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_22\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_one_hot_15\/main_0 29.900 MHz 33.445 758.222
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 8.064
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_15\/main_0 10.255
macrocell25 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_15\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_one_hot_51\/main_0 29.900 MHz 33.445 758.222
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 8.064
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_51\/main_0 10.255
macrocell61 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_51\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_one_hot_61\/main_0 29.900 MHz 33.445 758.222
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,1) 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_5\ \ADC:AMuxHw_2_Decoder_old_id_5\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 8.064
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_61\/main_0 10.255
macrocell71 U(3,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_61\ SETUP 3.510
Clock Skew 0.000
\ADC:AMuxHw_2_Decoder_old_id_0\/q \ADC:AMuxHw_2_Decoder_one_hot_13\/main_0 29.976 MHz 33.360 758.307
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,5) 1 \ADC:AMuxHw_2_Decoder_old_id_0\ \ADC:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC:AMuxHw_2_Decoder_old_id_0\ \ADC:AMuxHw_2_Decoder_old_id_0\/q \ADC:AMuxHw_2_Decoder_is_active_split\/main_10 7.408
macrocell1 U(2,3) 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/main_10 \ADC:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active_split\ \ADC:AMuxHw_2_Decoder_is_active_split\/q \ADC:AMuxHw_2_Decoder_is_active\/main_8 3.666
macrocell2 U(2,1) 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/main_8 \ADC:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC:AMuxHw_2_Decoder_is_active\ \ADC:AMuxHw_2_Decoder_is_active\/q \ADC:AMuxHw_2_Decoder_one_hot_13\/main_0 10.826
macrocell23 U(2,5) 1 \ADC:AMuxHw_2_Decoder_one_hot_13\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_664/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_2 135.501 MHz 7.380 34.287
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,4) 1 Net_664 Net_664/clock_0 Net_664/q 1.250
Route 1 Net_664 Net_664/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_2 2.620
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q Net_664/main_0 135.851 MHz 7.361 34.306
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q Net_664/main_0 2.601
macrocell74 U(2,4) 1 Net_664 SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:nrq_reg\/main_0 135.851 MHz 7.361 34.306
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:nrq_reg\/main_0 2.601
macrocell76 U(2,4) 1 \ADC:bSAR_SEQ:nrq_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Button_17_22(1)/fb Net_939_1/main_0 84.027 MHz 11.901 29.766
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell28 P1[3] 1 Button_17_22(1) Button_17_22(1)/in_clock Button_17_22(1)/fb 2.397
Route 1 Net_946_1 Button_17_22(1)/fb Net_939_1/main_0 5.994
macrocell86 U(2,1) 1 Net_939_1 SETUP 3.510
Clock Skew 0.000
Button_17_22(0)/fb Net_939_0/main_0 84.983 MHz 11.767 29.900
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell27 P1[2] 1 Button_17_22(0) Button_17_22(0)/in_clock Button_17_22(0)/fb 2.996
Route 1 Net_946_0 Button_17_22(0)/fb Net_939_0/main_0 5.261
macrocell85 U(0,2) 1 Net_939_0 SETUP 3.510
Clock Skew 0.000
Button_9_16(6)/fb Net_938_6/main_0 86.708 MHz 11.533 30.134
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell25 P2[6] 1 Button_9_16(6) Button_9_16(6)/in_clock Button_9_16(6)/fb 2.769
Route 1 Net_940_6 Button_9_16(6)/fb Net_938_6/main_0 5.254
macrocell97 U(0,3) 1 Net_938_6 SETUP 3.510
Clock Skew 0.000
Button_9_16(5)/fb Net_938_5/main_0 87.612 MHz 11.414 30.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell24 P2[5] 1 Button_9_16(5) Button_9_16(5)/in_clock Button_9_16(5)/fb 2.667
Route 1 Net_940_5 Button_9_16(5)/fb Net_938_5/main_0 5.237
macrocell96 U(0,3) 1 Net_938_5 SETUP 3.510
Clock Skew 0.000
Button_17_22(3)/fb Net_939_3/main_0 88.113 MHz 11.349 30.318
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell30 P1[5] 1 Button_17_22(3) Button_17_22(3)/in_clock Button_17_22(3)/fb 2.601
Route 1 Net_946_3 Button_17_22(3)/fb Net_939_3/main_0 5.238
macrocell88 U(0,2) 1 Net_939_3 SETUP 3.510
Clock Skew 0.000
Button_9_16(7)/fb Net_938_7/main_0 88.339 MHz 11.320 30.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell26 P2[7] 1 Button_9_16(7) Button_9_16(7)/in_clock Button_9_16(7)/fb 2.498
Route 1 Net_940_7 Button_9_16(7)/fb Net_938_7/main_0 5.312
macrocell98 U(0,3) 1 Net_938_7 SETUP 3.510
Clock Skew 0.000
Button_9_16(3)/fb Net_938_3/main_0 88.660 MHz 11.279 30.388
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell22 P2[3] 1 Button_9_16(3) Button_9_16(3)/in_clock Button_9_16(3)/fb 2.515
Route 1 Net_940_3 Button_9_16(3)/fb Net_938_3/main_0 5.254
macrocell94 U(0,3) 1 Net_938_3 SETUP 3.510
Clock Skew 0.000
Button_9_16(2)/fb Net_938_2/main_0 88.708 MHz 11.273 30.394
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell21 P2[2] 1 Button_9_16(2) Button_9_16(2)/in_clock Button_9_16(2)/fb 2.503
Route 1 Net_940_2 Button_9_16(2)/fb Net_938_2/main_0 5.260
macrocell93 U(0,3) 1 Net_938_2 SETUP 3.510
Clock Skew 0.000
Button_1_8(3)/fb Net_909_3/main_0 88.715 MHz 11.272 30.395
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P3[3] 1 Button_1_8(3) Button_1_8(3)/in_clock Button_1_8(3)/fb 3.163
Route 1 Net_910_3 Button_1_8(3)/fb Net_909_3/main_0 4.599
macrocell80 U(3,0) 1 Net_909_3 SETUP 3.510
Clock Skew 0.000
Button_17_22(4)/fb Net_939_4/main_0 88.865 MHz 11.253 30.414
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell31 P1[6] 1 Button_17_22(4) Button_17_22(4)/in_clock Button_17_22(4)/fb 2.485
Route 1 Net_946_4 Button_17_22(4)/fb Net_939_4/main_0 5.258
macrocell89 U(0,2) 1 Net_939_4 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC:Sync:genblk1[0]:INST\/out \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_1 134.354 MHz 7.443 34.224
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \ADC:Sync:genblk1[0]:INST\ \ADC:Sync:genblk1[0]:INST\/clock \ADC:Sync:genblk1[0]:INST\/out 1.020
Route 1 \ADC:Net_3935\ \ADC:Sync:genblk1[0]:INST\/out \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_1 2.913
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_0 135.851 MHz 7.361 34.306
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_0 2.601
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:EOCSts\/clk_en 2.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,5) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC:bSAR_SEQ:enable\ \ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:EOCSts\/clk_en 2.298
statuscell1 U(3,5) 1 \ADC:bSAR_SEQ:EOCSts\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_4 \ADC:AMuxHw_2_Decoder_old_id_4\/main_0 3.518
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_4 0.620
Route 1 \ADC:ch_addr_4\ \ADC:bSAR_SEQ:ChannelCounter\/count_4 \ADC:AMuxHw_2_Decoder_old_id_4\/main_0 2.898
macrocell5 U(2,5) 1 \ADC:AMuxHw_2_Decoder_old_id_4\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:nrq_reg\/q Net_664/main_1 3.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell76 U(2,4) 1 \ADC:bSAR_SEQ:nrq_reg\ \ADC:bSAR_SEQ:nrq_reg\/clock_0 \ADC:bSAR_SEQ:nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:nrq_reg\ \ADC:bSAR_SEQ:nrq_reg\/q Net_664/main_1 2.303
macrocell74 U(2,4) 1 Net_664 HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:ChannelCounter\/clk_en 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,5) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC:bSAR_SEQ:enable\ \ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:ChannelCounter\/clk_en 3.198
count7cell U(2,4) 1 \ADC:bSAR_SEQ:ChannelCounter\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_0 Net_664/clk_en 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,5) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC:bSAR_SEQ:enable\ \ADC:bSAR_SEQ:CtrlReg\/control_0 Net_664/clk_en 3.198
macrocell74 U(2,4) 1 Net_664 HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:nrq_reg\/clk_en 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,5) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_0 0.360
Route 1 \ADC:bSAR_SEQ:enable\ \ADC:bSAR_SEQ:CtrlReg\/control_0 \ADC:bSAR_SEQ:nrq_reg\/clk_en 3.198
macrocell76 U(2,4) 1 \ADC:bSAR_SEQ:nrq_reg\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:CtrlReg\/control_1 \ADC:bSAR_SEQ:ChannelCounter\/load 3.606
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,5) 1 \ADC:bSAR_SEQ:CtrlReg\ \ADC:bSAR_SEQ:CtrlReg\/clock \ADC:bSAR_SEQ:CtrlReg\/control_1 0.360
Route 1 \ADC:bSAR_SEQ:load_period\ \ADC:bSAR_SEQ:CtrlReg\/control_1 \ADC:bSAR_SEQ:ChannelCounter\/load 3.246
count7cell U(2,4) 1 \ADC:bSAR_SEQ:ChannelCounter\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_1 \ADC:AMuxHw_2_Decoder_old_id_1\/main_0 3.816
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_1 0.620
Route 1 \ADC:ch_addr_1\ \ADC:bSAR_SEQ:ChannelCounter\/count_1 \ADC:AMuxHw_2_Decoder_old_id_1\/main_0 3.196
macrocell8 U(2,5) 1 \ADC:AMuxHw_2_Decoder_old_id_1\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_0 \ADC:AMuxHw_2_Decoder_old_id_0\/main_0 3.841
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_0 0.620
Route 1 \ADC:ch_addr_0\ \ADC:bSAR_SEQ:ChannelCounter\/count_0 \ADC:AMuxHw_2_Decoder_old_id_0\/main_0 3.221
macrocell9 U(2,5) 1 \ADC:AMuxHw_2_Decoder_old_id_0\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:ChannelCounter\/count_3 \ADC:AMuxHw_2_Decoder_old_id_3\/main_0 3.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \ADC:bSAR_SEQ:ChannelCounter\ \ADC:bSAR_SEQ:ChannelCounter\/clock \ADC:bSAR_SEQ:ChannelCounter\/count_3 0.620
Route 1 \ADC:ch_addr_3\ \ADC:bSAR_SEQ:ChannelCounter\/count_3 \ADC:AMuxHw_2_Decoder_old_id_3\/main_0 3.222
macrocell6 U(2,5) 1 \ADC:AMuxHw_2_Decoder_old_id_3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_664/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_2 3.870
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,4) 1 Net_664 Net_664/clock_0 Net_664/q 1.250
Route 1 Net_664 Net_664/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_2 2.620
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q Net_664/main_0 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q Net_664/main_0 2.601
macrocell74 U(2,4) 1 Net_664 HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:nrq_reg\/main_0 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
Route 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:nrq_reg\/main_0 2.601
macrocell76 U(2,4) 1 \ADC:bSAR_SEQ:nrq_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Button_1_8(6)/fb Net_909_6/main_0 6.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell13 P3[6] 1 Button_1_8(6) Button_1_8(6)/in_clock Button_1_8(6)/fb 1.599
Route 1 Net_910_6 Button_1_8(6)/fb Net_909_6/main_0 4.611
macrocell83 U(3,0) 1 Net_909_6 HOLD 0.000
Clock Skew 0.000
Button_1_8(1)/fb Net_909_1/main_0 6.279
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P3[1] 1 Button_1_8(1) Button_1_8(1)/in_clock Button_1_8(1)/fb 1.661
Route 1 Net_910_1 Button_1_8(1)/fb Net_909_1/main_0 4.618
macrocell78 U(3,0) 1 Net_909_1 HOLD 0.000
Clock Skew 0.000
Button_1_8(2)/fb Net_909_2/main_0 6.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[2] 1 Button_1_8(2) Button_1_8(2)/in_clock Button_1_8(2)/fb 1.852
Route 1 Net_910_2 Button_1_8(2)/fb Net_909_2/main_0 4.612
macrocell79 U(3,0) 1 Net_909_2 HOLD 0.000
Clock Skew 0.000
Button_1_8(7)/fb Net_909_7/main_0 6.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell14 P3[7] 1 Button_1_8(7) Button_1_8(7)/in_clock Button_1_8(7)/fb 1.948
Route 1 Net_910_7 Button_1_8(7)/fb Net_909_7/main_0 4.602
macrocell84 U(3,0) 1 Net_909_7 HOLD 0.000
Clock Skew 0.000
Button_1_8(5)/fb Net_909_5/main_0 6.659
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell12 P3[5] 1 Button_1_8(5) Button_1_8(5)/in_clock Button_1_8(5)/fb 2.064
Route 1 Net_910_5 Button_1_8(5)/fb Net_909_5/main_0 4.595
macrocell82 U(3,0) 1 Net_909_5 HOLD 0.000
Clock Skew 0.000
Button_1_8(4)/fb Net_909_4/main_0 6.771
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell11 P3[4] 1 Button_1_8(4) Button_1_8(4)/in_clock Button_1_8(4)/fb 2.191
Route 1 Net_910_4 Button_1_8(4)/fb Net_909_4/main_0 4.580
macrocell81 U(3,0) 1 Net_909_4 HOLD 0.000
Clock Skew 0.000
Button_1_8(0)/fb Net_909_0/main_0 7.263
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P3[0] 1 Button_1_8(0) Button_1_8(0)/in_clock Button_1_8(0)/fb 2.685
Route 1 Net_910_0 Button_1_8(0)/fb Net_909_0/main_0 4.578
macrocell77 U(3,0) 1 Net_909_0 HOLD 0.000
Clock Skew 0.000
Button_9_16(1)/fb Net_938_1/main_0 7.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell20 P2[1] 1 Button_9_16(1) Button_9_16(1)/in_clock Button_9_16(1)/fb 2.032
Route 1 Net_940_1 Button_9_16(1)/fb Net_938_1/main_0 5.253
macrocell92 U(0,3) 1 Net_938_1 HOLD 0.000
Clock Skew 0.000
Button_9_16(4)/fb Net_938_4/main_0 7.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell23 P2[4] 1 Button_9_16(4) Button_9_16(4)/in_clock Button_9_16(4)/fb 2.035
Route 1 Net_940_4 Button_9_16(4)/fb Net_938_4/main_0 5.302
macrocell95 U(0,3) 1 Net_938_4 HOLD 0.000
Clock Skew 0.000
Button_17_22(2)/fb Net_939_2/main_0 7.386
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell29 P1[4] 1 Button_17_22(2) Button_17_22(2)/in_clock Button_17_22(2)/fb 2.131
Route 1 Net_946_2 Button_17_22(2)/fb Net_939_2/main_0 5.255
macrocell87 U(0,2) 1 Net_939_2 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC:Sync:genblk1[0]:INST\/out \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_1 3.263
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \ADC:Sync:genblk1[0]:INST\ \ADC:Sync:genblk1[0]:INST\/clock \ADC:Sync:genblk1[0]:INST\/out 0.350
Route 1 \ADC:Net_3935\ \ADC:Sync:genblk1[0]:INST\/out \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_1 2.913
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
\ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_0 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/clock_0 \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q 1.250
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ \ADC:bSAR_SEQ:bus_clk_nrq_reg\/q \ADC:bSAR_SEQ:bus_clk_nrq_reg\/main_0 2.601
macrocell75 U(2,4) 1 \ADC:bSAR_SEQ:bus_clk_nrq_reg\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\OutputReg2:Sync:ctrl_reg\/control_2 Out_11(0)_PAD 25.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,2) 1 \OutputReg2:Sync:ctrl_reg\ \OutputReg2:Sync:ctrl_reg\/busclk \OutputReg2:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_538 \OutputReg2:Sync:ctrl_reg\/control_2 Out_11(0)/pin_input 7.328
iocell43 P12[6] 1 Out_11(0) Out_11(0)/pin_input Out_11(0)/pad_out 16.220
Route 1 Out_11(0)_PAD Out_11(0)/pad_out Out_11(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg2:Sync:ctrl_reg\/control_1 Out_10(0)_PAD 25.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,2) 1 \OutputReg2:Sync:ctrl_reg\ \OutputReg2:Sync:ctrl_reg\/busclk \OutputReg2:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_537 \OutputReg2:Sync:ctrl_reg\/control_1 Out_10(0)/pin_input 7.328
iocell42 P12[5] 1 Out_10(0) Out_10(0)/pin_input Out_10(0)/pad_out 16.038
Route 1 Out_10(0)_PAD Out_10(0)/pad_out Out_10(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg1:Sync:ctrl_reg\/control_4 Out_5(0)_PAD 25.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \OutputReg1:Sync:ctrl_reg\ \OutputReg1:Sync:ctrl_reg\/busclk \OutputReg1:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_531 \OutputReg1:Sync:ctrl_reg\/control_4 Out_5(0)/pin_input 7.513
iocell37 P15[4] 1 Out_5(0) Out_5(0)/pin_input Out_5(0)/pad_out 15.848
Route 1 Out_5(0)_PAD Out_5(0)/pad_out Out_5(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg1:Sync:ctrl_reg\/control_5 Out_6(0)_PAD 25.336
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \OutputReg1:Sync:ctrl_reg\ \OutputReg1:Sync:ctrl_reg\/busclk \OutputReg1:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_532 \OutputReg1:Sync:ctrl_reg\/control_5 Out_6(0)/pin_input 7.361
iocell38 P15[5] 1 Out_6(0) Out_6(0)/pin_input Out_6(0)/pad_out 15.925
Route 1 Out_6(0)_PAD Out_6(0)/pad_out Out_6(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg2:Sync:ctrl_reg\/control_0 Out_9(0)_PAD 25.212
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,2) 1 \OutputReg2:Sync:ctrl_reg\ \OutputReg2:Sync:ctrl_reg\/busclk \OutputReg2:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_540 \OutputReg2:Sync:ctrl_reg\/control_0 Out_9(0)/pin_input 6.547
iocell41 P12[4] 1 Out_9(0) Out_9(0)/pin_input Out_9(0)/pad_out 16.615
Route 1 Out_9(0)_PAD Out_9(0)/pad_out Out_9(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg2:Sync:ctrl_reg\/control_3 Out_12(0)_PAD 24.917
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,2) 1 \OutputReg2:Sync:ctrl_reg\ \OutputReg2:Sync:ctrl_reg\/busclk \OutputReg2:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_539 \OutputReg2:Sync:ctrl_reg\/control_3 Out_12(0)/pin_input 5.900
iocell44 P12[7] 1 Out_12(0) Out_12(0)/pin_input Out_12(0)/pad_out 16.967
Route 1 Out_12(0)_PAD Out_12(0)/pad_out Out_12(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg1:Sync:ctrl_reg\/control_7 Out_8(0)_PAD 24.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \OutputReg1:Sync:ctrl_reg\ \OutputReg1:Sync:ctrl_reg\/busclk \OutputReg1:Sync:ctrl_reg\/control_7 2.050
Route 1 Net_534 \OutputReg1:Sync:ctrl_reg\/control_7 Out_8(0)/pin_input 5.847
iocell40 P12[3] 1 Out_8(0) Out_8(0)/pin_input Out_8(0)/pad_out 16.196
Route 1 Out_8(0)_PAD Out_8(0)/pad_out Out_8(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg1:Sync:ctrl_reg\/control_6 Out_7(0)_PAD 23.581
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \OutputReg1:Sync:ctrl_reg\ \OutputReg1:Sync:ctrl_reg\/busclk \OutputReg1:Sync:ctrl_reg\/control_6 2.050
Route 1 Net_533 \OutputReg1:Sync:ctrl_reg\/control_6 Out_7(0)/pin_input 5.865
iocell39 P12[2] 1 Out_7(0) Out_7(0)/pin_input Out_7(0)/pad_out 15.666
Route 1 Out_7(0)_PAD Out_7(0)/pad_out Out_7(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg1:Sync:ctrl_reg\/control_3 Out_4(0)_PAD 23.329
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \OutputReg1:Sync:ctrl_reg\ \OutputReg1:Sync:ctrl_reg\/busclk \OutputReg1:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_529 \OutputReg1:Sync:ctrl_reg\/control_3 Out_4(0)/pin_input 5.793
iocell36 P15[3] 1 Out_4(0) Out_4(0)/pin_input Out_4(0)/pad_out 15.486
Route 1 Out_4(0)_PAD Out_4(0)/pad_out Out_4(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg1:Sync:ctrl_reg\/control_2 Out_3(0)_PAD 22.973
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \OutputReg1:Sync:ctrl_reg\ \OutputReg1:Sync:ctrl_reg\/busclk \OutputReg1:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_528 \OutputReg1:Sync:ctrl_reg\/control_2 Out_3(0)/pin_input 5.819
iocell35 P15[2] 1 Out_3(0) Out_3(0)/pin_input Out_3(0)/pad_out 15.104
Route 1 Out_3(0)_PAD Out_3(0)/pad_out Out_3(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg1:Sync:ctrl_reg\/control_0 Out_1(0)_PAD 22.890
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \OutputReg1:Sync:ctrl_reg\ \OutputReg1:Sync:ctrl_reg\/busclk \OutputReg1:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_530 \OutputReg1:Sync:ctrl_reg\/control_0 Out_1(0)/pin_input 6.585
iocell33 P15[0] 1 Out_1(0) Out_1(0)/pin_input Out_1(0)/pad_out 14.255
Route 1 Out_1(0)_PAD Out_1(0)/pad_out Out_1(0)_PAD 0.000
Clock Clock path delay 0.000
\OutputReg1:Sync:ctrl_reg\/control_1 Out_2(0)_PAD 22.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \OutputReg1:Sync:ctrl_reg\ \OutputReg1:Sync:ctrl_reg\/busclk \OutputReg1:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_527 \OutputReg1:Sync:ctrl_reg\/control_1 Out_2(0)/pin_input 5.822
iocell34 P15[1] 1 Out_2(0) Out_2(0)/pin_input Out_2(0)/pad_out 14.429
Route 1 Out_2(0)_PAD Out_2(0)/pad_out Out_2(0)_PAD 0.000
Clock Clock path delay 0.000