Static Timing Analysis

Project : 7eyes_Prox_Beep
Build Time : 08/17/20 15:34:08
Device : CY8C4247AZI-M485
Temperature : -40C - 85C
VDDA_0 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDD_0 : 3.30
VDDD_1 : 3.30
VDDIO : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CapSense_SampleClk(FFB) CapSense_SampleClk(FFB) 188.235 kHz 188.235 kHz N/A
CapSense_SenseClk(FFB) CapSense_SenseClk(FFB) 188.235 kHz 188.235 kHz N/A
Clock_1(FFB) Clock_1(FFB) 10.000 kHz 10.000 kHz N/A
\PWM_1:cy_m0s8_tcpwm_1\/line Clock_1(FFB) UNKNOWN UNKNOWN 118.147 MHz
Clock_2(FFB) Clock_2(FFB) 1.000 MHz 1.000 MHz N/A
CyHFClk CyHFClk 48.000 MHz 48.000 MHz N/A
CapSense_SampleClk CyHFClk 188.235 kHz 188.235 kHz N/A
CapSense_SenseClk CyHFClk 188.235 kHz 188.235 kHz N/A
Clock_1 CyHFClk 10.000 kHz 10.000 kHz N/A
Clock_2 CyHFClk 1.000 MHz 1.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFClk CyLFClk 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySysClk CySysClk 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 200000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_283_0/q Net_283_2/main_0 118.147 MHz 8.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_283_2/main_0 3.704
macrocell6 U(1,0) 1 Net_283_2 SETUP 3.510
Clock Skew 0.000
Net_283_0/q Net_283_1/main_0 118.147 MHz 8.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_283_1/main_0 3.704
macrocell7 U(1,0) 1 Net_283_1 SETUP 3.510
Clock Skew 0.000
Net_283_1/q Net_283_2/main_2 137.137 MHz 7.292
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,0) 1 Net_283_1 Net_283_1/clock_0 Net_283_1/q 1.250
Route 1 Net_283_1 Net_283_1/q Net_283_2/main_2 2.532
macrocell6 U(1,0) 1 Net_283_2 SETUP 3.510
Clock Skew 0.000
Net_283_1/q Net_283_1/main_2 137.137 MHz 7.292
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,0) 1 Net_283_1 Net_283_1/clock_0 Net_283_1/q 1.250
macrocell7 U(1,0) 1 Net_283_1 Net_283_1/q Net_283_1/main_2 2.532
macrocell7 U(1,0) 1 Net_283_1 SETUP 3.510
Clock Skew 0.000
Net_283_2/q Net_283_2/main_1 137.193 MHz 7.289
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_283_2 Net_283_2/clock_0 Net_283_2/q 1.250
macrocell6 U(1,0) 1 Net_283_2 Net_283_2/q Net_283_2/main_1 2.529
macrocell6 U(1,0) 1 Net_283_2 SETUP 3.510
Clock Skew 0.000
Net_283_2/q Net_283_1/main_1 137.193 MHz 7.289
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_283_2 Net_283_2/clock_0 Net_283_2/q 1.250
Route 1 Net_283_2 Net_283_2/q Net_283_1/main_1 2.529
macrocell7 U(1,0) 1 Net_283_1 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_283_2/q Net_283_2/main_1 3.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_283_2 Net_283_2/clock_0 Net_283_2/q 1.250
macrocell6 U(1,0) 1 Net_283_2 Net_283_2/q Net_283_2/main_1 2.529
macrocell6 U(1,0) 1 Net_283_2 HOLD 0.000
Clock Skew 0.000
Net_283_2/q Net_283_1/main_1 3.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_283_2 Net_283_2/clock_0 Net_283_2/q 1.250
Route 1 Net_283_2 Net_283_2/q Net_283_1/main_1 2.529
macrocell7 U(1,0) 1 Net_283_1 HOLD 0.000
Clock Skew 0.000
Net_283_1/q Net_283_2/main_2 3.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,0) 1 Net_283_1 Net_283_1/clock_0 Net_283_1/q 1.250
Route 1 Net_283_1 Net_283_1/q Net_283_2/main_2 2.532
macrocell6 U(1,0) 1 Net_283_2 HOLD 0.000
Clock Skew 0.000
Net_283_1/q Net_283_1/main_2 3.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,0) 1 Net_283_1 Net_283_1/clock_0 Net_283_1/q 1.250
macrocell7 U(1,0) 1 Net_283_1 Net_283_1/q Net_283_1/main_2 2.532
macrocell7 U(1,0) 1 Net_283_1 HOLD 0.000
Clock Skew 0.000
Net_283_0/q Net_283_2/main_0 4.954
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_283_2/main_0 3.704
macrocell6 U(1,0) 1 Net_283_2 HOLD 0.000
Clock Skew 0.000
Net_283_0/q Net_283_1/main_0 4.954
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_283_1/main_0 3.704
macrocell7 U(1,0) 1 Net_283_1 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_2(FFB)
Source Destination Delay (ns)
\PWM_2:cy_m0s8_tcpwm_1\/line Beep(0)_PAD 17.350
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,4) 1 \PWM_2:cy_m0s8_tcpwm_1\ \PWM_2:cy_m0s8_tcpwm_1\/clock \PWM_2:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_82 \PWM_2:cy_m0s8_tcpwm_1\/line Beep(0)/pin_input 1.000
iocell8 P2[0] 1 Beep(0) Beep(0)/pin_input Beep(0)/pad_out 16.350
Route 1 Beep(0)_PAD Beep(0)/pad_out Beep(0)_PAD 0.000
Clock Clock path delay 0.000
+ \PWM_1:cy_m0s8_tcpwm_1\/line
Source Destination Delay (ns)
Net_283_0/q Pin6(0)_PAD 37.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_16/main_0 3.726
macrocell1 U(1,0) 1 Net_16 Net_16/main_0 Net_16/q 3.350
Route 1 Net_16 Net_16/q Pin6(0)/pin_input 5.441
iocell1 P3[0] 1 Pin6(0) Pin6(0)/pin_input Pin6(0)/pad_out 17.730
Route 1 Pin6(0)_PAD Pin6(0)/pad_out Pin6(0)_PAD 0.000
Clock Clock path delay 6.317
Net_283_0/q Pin7(0)_PAD 36.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_14/main_0 3.704
macrocell3 U(1,0) 1 Net_14 Net_14/main_0 Net_14/q 3.350
Route 1 Net_14 Net_14/q Pin7(0)/pin_input 5.451
iocell2 P3[1] 1 Pin7(0) Pin7(0)/pin_input Pin7(0)/pad_out 16.860
Route 1 Pin7(0)_PAD Pin7(0)/pad_out Pin7(0)_PAD 0.000
Clock Clock path delay 6.317
Net_283_0/q Pin1(0)_PAD 35.649
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_14/main_0 3.704
macrocell3 U(1,0) 1 Net_14 Net_14/main_0 Net_14/q 3.350
Route 1 Net_14 Net_14/q Pin1(0)/pin_input 5.808
iocell7 P1[3] 1 Pin1(0) Pin1(0)/pin_input Pin1(0)/pad_out 15.220
Route 1 Pin1(0)_PAD Pin1(0)/pad_out Pin1(0)_PAD 0.000
Clock Clock path delay 6.317
Net_283_0/q Pin5(0)_PAD 35.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_15/main_0 3.726
macrocell2 U(1,0) 1 Net_15 Net_15/main_0 Net_15/q 3.350
Route 1 Net_15 Net_15/q Pin5(0)/pin_input 5.753
iocell5 P1[2] 1 Pin5(0) Pin5(0)/pin_input Pin5(0)/pad_out 15.090
Route 1 Pin5(0)_PAD Pin5(0)/pad_out Pin5(0)_PAD 0.000
Clock Clock path delay 6.317
Net_283_0/q Pin2(0)_PAD 35.452
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_16/main_0 3.726
macrocell1 U(1,0) 1 Net_16 Net_16/main_0 Net_16/q 3.350
Route 1 Net_16 Net_16/q Pin2(0)/pin_input 6.079
iocell6 P0[2] 1 Pin2(0) Pin2(0)/pin_input Pin2(0)/pad_out 14.730
Route 1 Pin2(0)_PAD Pin2(0)/pad_out Pin2(0)_PAD 0.000
Clock Clock path delay 6.317
Net_283_0/q Pin3(0)_PAD 34.996
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Net_15/main_0 3.726
macrocell2 U(1,0) 1 Net_15 Net_15/main_0 Net_15/q 3.350
Route 1 Net_15 Net_15/q Pin3(0)/pin_input 5.753
iocell3 P1[0] 1 Pin3(0) Pin3(0)/pin_input Pin3(0)/pad_out 14.600
Route 1 Pin3(0)_PAD Pin3(0)/pad_out Pin3(0)_PAD 0.000
Clock Clock path delay 6.317
Net_283_0/q Pin4(0)_PAD 28.754
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_283_0 Net_283_0/clock_0 Net_283_0/q 1.250
Route 1 Net_283_0 Net_283_0/q Pin4(0)/pin_input 6.007
iocell4 P1[1] 1 Pin4(0) Pin4(0)/pin_input Pin4(0)/pad_out 15.180
Route 1 Pin4(0)_PAD Pin4(0)/pad_out Pin4(0)_PAD 0.000
Clock Clock path delay 6.317