/*
 * Linker script
 */

// size of the DSPR RAM for each core
#define DSPR_CORE0 184k

// size of the PFLASH
#define PFLASH_SIZE 2M

// reserved sections in PFLASH
section_setup mpe:vtc:linear
{
  // According to Tasking compiler user guide the reserved keyword is used, like
  // reserved start_address .. end_address;
  // For compiler v4.x we had to add +1 to end_address cause the linker tries
  // to link to adress 0xa001bfff.

	reserved 0x80014000 .. 0x80018000;  // S5 Tuning Protection
	reserved 0x80018000 .. 0x8001c000;  // S6 HSM
	reserved 0x80060000 .. 0x80070000;  // S16 HSM
	reserved 0x80070000 .. 0x80080000;  // S17 HSM
}

// Minimal TC29XT CPU description for Tasking linker.
//
// This file contains a stripped-down CPU description for the Tasking
// linker. It was created using a trial-and-error
// method, starting with an empty file and adding only the portions
// that the linker complained about.

architecture TC
{
	endianness
	{
		little;
	}

	space linear
	{
		id = 1;
		mau = 8;

		map (src_offset=0x00000000, dest_offset=0x00000000, size=4G, dest=bus:fpi_bus);

		copytable (align = 1 << 2, copy_unit = 1, dest = linear);
	}

	bus fpi_bus
	{
		mau = 8;
		width = 32;
	}
}

architecture TC1V1.6.X extends TC
{
}

processor mpe
{
	derivative = tcxxx;
}

derivative tcxxx
{
	core vtc
	{
		architecture = TC1V1.6.X;
	}

	bus fpi_bus
	{
		mau = 8;
		width = 32;
		map (dest=bus:vtc:fpi_bus, dest_offset=0, size=4G);
	}
}

#define NCSA_C0 256

// DSPR - Space used for CSA
#define INTRAM_CORE0 (DSPR_CORE0 - NCSA_C0*64)

// size of the initial memory portion int_rom_vect used for vectors
#define INT_ROM_VECT_SIZE 20k

// Flash ROM at 0x80000000, PMU0 (mapped to seg. 8 for cached access)
memory int_rom_vect
{
	mau = 8;
	size = INT_ROM_VECT_SIZE;
	type = rom;
	map (dest=bus:mpe:fpi_bus, dest_offset=0x80000000, size=INT_ROM_VECT_SIZE);
}

memory int_rom
{
	mau = 8;
	size = (PFLASH_SIZE - INT_ROM_VECT_SIZE);
	type = rom;
	map (dest=bus:mpe:fpi_bus,
		dest_offset=(0x80000000+INT_ROM_VECT_SIZE),
		size=(PFLASH_SIZE - INT_ROM_VECT_SIZE));
}

// internal DSPRs of the different cores
memory int_ram_core0
{
	mau = 8;
	size = INTRAM_CORE0;
	type = ram;
	map (dest=bus:mpe:fpi_bus, dest_offset=0x70000000, size=INTRAM_CORE0);
}

// Where the CSA memory is located:
// MK_RSA_MK_Csa_Cx is the base of the CSA block for core x
// MK_RLA_MK_Csa_Cx is the limit - i.e. the first address that won't be - for core x
// used as a CSA
//
// These must be aligned on 64-byte boundaries (lower 6 bits all zero),
// otherwise the initialisation function will round them and you might end
// up with fewer CSAs than you expect.
section_layout mpe:vtc:linear
{
	"BOARD_C0_RAM_BEG"  = addressof(mem:int_ram_core0);
	"BOARD_C0_URAM_END" = "BOARD_C0_RAM_BEG" + sizeof(mem:int_ram_core0);

	"MK_RSA_MK_Csa_C0"  := 0xd0000000 + INTRAM_CORE0;
	"MK_RLA_MK_Csa_C0"  := 0xd0000000 + DSPR_CORE0;
#ifdef DSPR_CORE1
	"BOARD_C1_RAM_BEG"   = addressof(mem:int_ram_core1);
	"BOARD_C1_URAM_END"  = "BOARD_C1_RAM_BEG" + sizeof(mem:int_ram_core1);

	"MK_RSA_MK_Csa_C1"  := 0xd0000000 + INTRAM_CORE1;
	"MK_RLA_MK_Csa_C1"  := 0xd0000000 + DSPR_CORE1;
#endif
#ifdef DSPR_CORE2
	"BOARD_C2_RAM_BEG"   = addressof(mem:int_ram_core2);
	"BOARD_C2_URAM_END"  = "BOARD_C2_RAM_BEG" + sizeof(mem:int_ram_core2);

	"MK_RSA_MK_Csa_C2"  := 0xd0000000 + INTRAM_CORE2;
	"MK_RLA_MK_Csa_C2"  := 0xd0000000 + DSPR_CORE2;
#endif

	/* Symbols of memory regions not bound to any object file */
	"MK_RSA_MK_Rom"       = addressof(mem:int_rom_vect); /* Flash */
	"MK_RLA_MK_Rom"       = addressof(mem:int_rom) + sizeof(mem:int_rom);
	"MK_RSA_MK_GlobalRam" = 0x50000000;
	"MK_RLA_MK_GlobalRam" = 0x80000000;
	"MK_RSA_MK_Io"        = 0xF0000000; /* I/O */
	"MK_RLA_MK_Io"        = 0xFF120000;
	"MK_RSA_MK_OsIo"      = 0xF0000000; /* OS I/O (STM only!!!) */
	"MK_RLA_MK_OsIo"      = 0xF0000300;

	/* Symbols for the initialisation of private data areas. */
	"MK_INITIAL_A0"     := 0;
	"MK_INITIAL_A1"     := 0;
	"MK_INITIAL_A8"     := 0; /* reserved for OS use */
}
section_layout mpe:vtc:linear
{
	
	group (contiguous, ordered, run_addr = mem:int_rom_vect)
	{
		/*
		 * Output section text.bootword (Type RESET)
		*/
		group (align=4)
		{
			section "text.bootword" (fill=0, attributes=rx, blocksize=4)
			{
				select "MK_bootword";
				select "MK_bootword.*";
			}
		}

		/*
		 * Output section text.reset (Type RESET)
		*/
		group (align=4)
		{
			section "text.reset" (fill=0, attributes=rx, blocksize=4)
			{
				select "MK_reset";
				select "MK_reset.*";
			}
		}

		/*
		 * Output section text.vectors (Type RESET)
		*/
		group (align=4)
		{
			section "text.vectors" (fill=0, attributes=rx, blocksize=4)
			{
				select "MK_exctable";
				select "MK_exctable.*";
			}
		}

	}
	
	group (contiguous, ordered, run_addr = mem:int_rom)
	{
		/*
		 * Output section text (Type TEXT)
		*/
		group (align=32)
		{
			section "text" (fill=0, attributes=rx, blocksize=32)
			{
				select ".text";
				select ".text.*";
				select ".mk_text";
				select ".mk_text.*";
				select ".os_text";
				select ".os_text.*";
				select ".rdata";
				select ".rdata.*";
			}
		}

		/*
		 * Output section rodata (Type RODATA)
		*/
		group (align=32)
		{
			section "rodata" (fill=0, attributes=r, blocksize=32)
			{
				select ".rodata";
				select ".rodata.*";
				select ".zrodata";
				select ".zrodata.*";
				select ".ldata";
				select ".ldata.*";
			}
		}
		"__GLBL_RODATA_END" = "_lc_ue_rodata";

	}
	
	group (contiguous, ordered, run_addr = mem:int_ram_core0)
	{
		/*
		 * Stacks on core 0
		*/
		/*
		 * Output section mk_stack_MK_c0_kernelStack (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_c0_kernelStack" (attributes=rw, blocksize=8)
			{
				select ".bss.Mk_c0_kernel_stack.*";
				select ".zbss.Mk_c0_kernel_stack.*";
				select ".sbss.Mk_c0_kernel_stack.*";
			}
		}
		"MK_RSA_MK_c0_kernelStack" = "_lc_ub_mk_stack_MK_c0_kernelStack";
		"MK_RLA_MK_c0_kernelStack" = "_lc_ue_mk_stack_MK_c0_kernelStack";

		/*
		 * Output section mk_stack_MK_c0_aux1Stack (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_c0_aux1Stack" (attributes=rw, blocksize=8)
			{
				select ".bss.Mk_c0_aux1_stack.*";
				select ".zbss.Mk_c0_aux1_stack.*";
				select ".sbss.Mk_c0_aux1_stack.*";
			}
		}
		"MK_RSA_MK_c0_aux1Stack" = "_lc_ub_mk_stack_MK_c0_aux1Stack";
		"MK_RLA_MK_c0_aux1Stack" = "_lc_ue_mk_stack_MK_c0_aux1Stack";

		/*
		 * Output section mk_stack_MK_c0_aux2Stack (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_c0_aux2Stack" (attributes=rw, blocksize=8)
			{
				select ".bss.Mk_c0_aux2_stack.*";
				select ".zbss.Mk_c0_aux2_stack.*";
				select ".sbss.Mk_c0_aux2_stack.*";
			}
		}
		"MK_RSA_MK_c0_aux2Stack" = "_lc_ub_mk_stack_MK_c0_aux2Stack";
		"MK_RLA_MK_c0_aux2Stack" = "_lc_ue_mk_stack_MK_c0_aux2Stack";

		/*
		 * Output section mk_stack_MK_c0_idleshutdownStack (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_c0_idleshutdownStack" (attributes=rw, blocksize=8)
			{
				select ".bss.Mk_c0_idleshutdown_stack.*";
				select ".zbss.Mk_c0_idleshutdown_stack.*";
				select ".sbss.Mk_c0_idleshutdown_stack.*";
			}
		}
		"MK_RSA_MK_c0_idleshutdownStack" = "_lc_ub_mk_stack_MK_c0_idleshutdownStack";
		"MK_RLA_MK_c0_idleshutdownStack" = "_lc_ue_mk_stack_MK_c0_idleshutdownStack";

		/*
		 * Output section mk_stack_MK_c0_blockerStack (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_c0_blockerStack" (attributes=rw, blocksize=8)
			{
				select ".bss.Mk_c0_blocker_stack.*";
				select ".zbss.Mk_c0_blocker_stack.*";
				select ".sbss.Mk_c0_blocker_stack.*";
			}
		}
		"MK_RSA_MK_c0_blockerStack" = "_lc_ub_mk_stack_MK_c0_blockerStack";
		"MK_RLA_MK_c0_blockerStack" = "_lc_ue_mk_stack_MK_c0_blockerStack";

		/*
		 * Output section mk_stack_MK_c0_errorhookStack (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_c0_errorhookStack" (attributes=rw, blocksize=8)
			{
				select ".bss.Mk_c0_errorhook_stack.*";
				select ".zbss.Mk_c0_errorhook_stack.*";
				select ".sbss.Mk_c0_errorhook_stack.*";
			}
		}
		"MK_RSA_MK_c0_errorhookStack" = "_lc_ub_mk_stack_MK_c0_errorhookStack";
		"MK_RLA_MK_c0_errorhookStack" = "_lc_ue_mk_stack_MK_c0_errorhookStack";

		/*
		 * Output section mk_stack_MK_c0_protectionHookStack (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_c0_protectionHookStack" (attributes=rw, blocksize=8)
			{
				select ".bss.Mk_c0_protectionhook_stack.*";
				select ".zbss.Mk_c0_protectionhook_stack.*";
				select ".sbss.Mk_c0_protectionhook_stack.*";
			}
		}
		"MK_RSA_MK_c0_protectionHookStack" = "_lc_ub_mk_stack_MK_c0_protectionHookStack";
		"MK_RLA_MK_c0_protectionHookStack" = "_lc_ue_mk_stack_MK_c0_protectionHookStack";

		/*
		 * Output section mk_stack_MK_threadStack0_slot0 (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_threadStack0_slot0" (attributes=rw, blocksize=8)
			{
				select ".bss.mk_stack_MK_threadStack0_slot0";
				select ".bss.mk_stack_MK_threadStack0_slot0.*";
			}
		}
		"MK_RSA_MK_threadStack0_slot0" = "_lc_ub_mk_stack_MK_threadStack0_slot0";
		"MK_RLA_MK_threadStack0_slot0" = "_lc_ue_mk_stack_MK_threadStack0_slot0";

		/*
		 * Output section mk_stack_MK_threadStack0_slot1 (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_threadStack0_slot1" (attributes=rw, blocksize=8)
			{
				select ".bss.mk_stack_MK_threadStack0_slot1";
				select ".bss.mk_stack_MK_threadStack0_slot1.*";
			}
		}
		"MK_RSA_MK_threadStack0_slot1" = "_lc_ub_mk_stack_MK_threadStack0_slot1";
		"MK_RLA_MK_threadStack0_slot1" = "_lc_ue_mk_stack_MK_threadStack0_slot1";

		/*
		 * Output section mk_stack_MK_threadStack0_slot2 (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_threadStack0_slot2" (attributes=rw, blocksize=8)
			{
				select ".bss.mk_stack_MK_threadStack0_slot2";
				select ".bss.mk_stack_MK_threadStack0_slot2.*";
			}
		}
		"MK_RSA_MK_threadStack0_slot2" = "_lc_ub_mk_stack_MK_threadStack0_slot2";
		"MK_RLA_MK_threadStack0_slot2" = "_lc_ue_mk_stack_MK_threadStack0_slot2";

		/*
		 * Output section mk_stack_MK_threadStack0_slot3 (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_threadStack0_slot3" (attributes=rw, blocksize=8)
			{
				select ".bss.mk_stack_MK_threadStack0_slot3";
				select ".bss.mk_stack_MK_threadStack0_slot3.*";
			}
		}
		"MK_RSA_MK_threadStack0_slot3" = "_lc_ub_mk_stack_MK_threadStack0_slot3";
		"MK_RLA_MK_threadStack0_slot3" = "_lc_ue_mk_stack_MK_threadStack0_slot3";

		/*
		 * Output section mk_stack_MK_threadStack0_slot4 (Type STACK)
		*/
		group (align=64, nocopy)
		{
			section "mk_stack_MK_threadStack0_slot4" (attributes=rw, blocksize=8)
			{
				select ".bss.mk_stack_MK_threadStack0_slot4";
				select ".bss.mk_stack_MK_threadStack0_slot4.*";
			}
		}
		"MK_RSA_MK_threadStack0_slot4" = "_lc_ub_mk_stack_MK_threadStack0_slot4";
		"MK_RLA_MK_threadStack0_slot4" = "_lc_ue_mk_stack_MK_threadStack0_slot4";

	}
	/*
	 * --------------------------------------------------------
	 * Memory regions for the MK and QM-OS data (core spanning)
	 * --------------------------------------------------------
	*/
	
	group (contiguous, ordered, run_addr = mem:int_ram_core0)
	{
		/*
		 * Output section MK_Ram_data (Type DATA)
		*/
		group (align=64)
		{
			section "MK_Ram_data" (attributes=rw, blocksize=64)
			{
				select ".data.Mk_*.*";
				select ".zdata.Mk_*.*";
				select ".sdata.Mk_*.*";
				select ".data.Ioc_data_kern_shared*.*";
				select ".zdata.Ioc_data_kern_shared*.*";
				select ".sdata.Ioc_data_kern_shared*.*";
				select ".data.Ioc_data_kern*.*";
				select ".zdata.Ioc_data_kern*.*";
				select ".sdata.Ioc_data_kern*.*";
			}
		}
		"MK_RSA_MK_Ram" = "_lc_ub_MK_Ram_data";

		/*
		 * Output section MK_Ram_bss (Type BSS)
		*/
		group (align=64, nocopy)
		{
			section "MK_Ram_bss" (attributes=rw, blocksize=32)
			{
				select ".bss.Mk_*.*";
				select ".zbss.Mk_*.*";
				select ".sbss.Mk_*.*";
				select ".lbss.Mk_*.*";
				select ".bss.Ioc_data_kern_shared*.*";
				select ".zbss.Ioc_data_kern_shared*.*";
				select ".sbss.Ioc_data_kern_shared*.*";
				select ".lbss.Ioc_data_kern_shared*.*";
				select ".bss.Ioc_data_kern*.*";
				select ".zbss.Ioc_data_kern*.*";
				select ".sbss.Ioc_data_kern*.*";
				select ".lbss.Ioc_data_kern*.*";
			}
		}
		"MK_BSA_MK_Ram" = "_lc_ub_MK_Ram_bss";
		"MK_RLA_MK_Ram" = "_lc_ue_MK_Ram_bss";

		/*
		 * Output section MK_OsRam_data (Type DATA)
		*/
		group (align=64)
		{
			section "MK_OsRam_data" (attributes=rw, blocksize=64)
			{
				select ".data.kern-*.*";
				select ".zdata.kern-*.*";
				select ".sdata.kern-*.*";
				select ".data.TRICORE-*.*";
				select ".zdata.TRICORE-*.*";
				select ".sdata.TRICORE-*.*";
				select ".data.Os_*.*";
				select ".zdata.Os_*.*";
				select ".sdata.Os_*.*";
				select ".data.core*.*";
				select ".zdata.core*.*";
				select ".sdata.core*.*";
				select ".data.shared.core*.*";
				select ".zdata.shared.core*.*";
				select ".sdata.shared.core*.*";
			}
		}
		"MK_RSA_MK_OsRam" = "_lc_ub_MK_OsRam_data";

		/*
		 * Output section MK_OsRam_bss (Type BSS)
		*/
		group (align=64, nocopy)
		{
			section "MK_OsRam_bss" (attributes=rw, blocksize=32)
			{
				select ".bss.kern-*.*";
				select ".zbss.kern-*.*";
				select ".sbss.kern-*.*";
				select ".lbss.kern-*.*";
				select ".bss.TRICORE-*.*";
				select ".zbss.TRICORE-*.*";
				select ".sbss.TRICORE-*.*";
				select ".lbss.TRICORE-*.*";
				select ".bss.Os_*.*";
				select ".zbss.Os_*.*";
				select ".sbss.Os_*.*";
				select ".lbss.Os_*.*";
				select ".bss.core*.*";
				select ".zbss.core*.*";
				select ".sbss.core*.*";
				select ".lbss.core*.*";
				select ".bss.shared.core*.*";
				select ".zbss.shared.core*.*";
				select ".sbss.shared.core*.*";
				select ".lbss.shared.core*.*";
			}
		}
		"MK_BSA_MK_OsRam" = "_lc_ub_MK_OsRam_bss";
		"MK_RLA_MK_OsRam" = "_lc_ue_MK_OsRam_bss";

	}
	
	group (contiguous, ordered, load_addr = mem:int_rom)
	{
		group (align=64)
		{
			section "initdata.MK_Ram_data" (fill=0, attributes=r, blocksize=64)
			{
				select "\[.data.Mk_*.*\]";
				select "\[.zdata.Mk_*.*\]";
				select "\[.sdata.Mk_*.*\]";
				select "\[.data.Ioc_data_kern_shared*.*\]";
				select "\[.zdata.Ioc_data_kern_shared*.*\]";
				select "\[.sdata.Ioc_data_kern_shared*.*\]";
				select "\[.data.Ioc_data_kern*.*\]";
				select "\[.zdata.Ioc_data_kern*.*\]";
				select "\[.sdata.Ioc_data_kern*.*\]";
			}
		}
		"MK_RDA_MK_Ram" = "_lc_ub_initdata.MK_Ram_data";

		group (align=64)
		{
			section "initdata.MK_OsRam_data" (fill=0, attributes=r, blocksize=64)
			{
				select "\[.data.kern-*.*\]";
				select "\[.zdata.kern-*.*\]";
				select "\[.sdata.kern-*.*\]";
				select "\[.data.TRICORE-*.*\]";
				select "\[.zdata.TRICORE-*.*\]";
				select "\[.sdata.TRICORE-*.*\]";
				select "\[.data.Os_*.*\]";
				select "\[.zdata.Os_*.*\]";
				select "\[.sdata.Os_*.*\]";
				select "\[.data.core*.*\]";
				select "\[.zdata.core*.*\]";
				select "\[.sdata.core*.*\]";
				select "\[.data.shared.core*.*\]";
				select "\[.zdata.shared.core*.*\]";
				select "\[.sdata.shared.core*.*\]";
			}
		}
		"MK_RDA_MK_OsRam" = "_lc_ub_initdata.MK_OsRam_data";

	}
	/*
	 * ---------------------------------------------------------
	 * Private memory regions of the application on core 0
	 * ---------------------------------------------------------
	*/
	
	group (contiguous, ordered, run_addr = mem:int_ram_core0)
	{
		/*
		 * Output section data_C0.App1 (Type DATA)
		*/
		group (align=64)
		{
			section "data_C0.App1" (attributes=rw, blocksize=64)
			{
				select ".data.App1_gen.*";
				select ".zdata.App1_gen.*";
				select ".sdata.App1_gen.*";
				select ".data.demo.*";
				select ".zdata.demo.*";
				select ".sdata.demo.*";
			}
		}
		"MK_RSA_App1" = "_lc_ub_data_C0.App1";

		/*
		 * Output section bss_C0.App1 (Type BSS)
		*/
		group (align=64, nocopy)
		{
			section "bss_C0.App1" (attributes=rw, blocksize=32)
			{
				select ".bss.App1_gen.*";
				select ".zbss.App1_gen.*";
				select ".sbss.App1_gen.*";
				select ".lbss.App1_gen.*";
				select ".bss.demo.*";
				select ".zbss.demo.*";
				select ".sbss.demo.*";
				select ".lbss.demo.*";
			}
		}
		"MK_BSA_App1" = "_lc_ub_bss_C0.App1";
		"MK_RLA_App1" = "_lc_ue_bss_C0.App1";

		"IOC_RSA_READABLE_App1" = "BOARD_C0_RAM_BEG";
		"IOC_RLA_READABLE_App1" = "BOARD_C0_URAM_END";

		/*
		 * Task Cyclic --- NO FILES
		*/
		"MK_RSA_Cyclic" = 0;
		"MK_RLA_Cyclic" = 0;
		"MK_RDA_Cyclic" = 0;
		"MK_BSA_Cyclic" = 0;

		/*
		 * Output section data_C0.OS_SYSTEM_0 (Type DATA)
		*/
		group (align=64)
		{
			section "data_C0.OS_SYSTEM_0" (attributes=rw, blocksize=64)
			{
				select ".data.OS_SYSTEM_0_gen.*";
				select ".zdata.OS_SYSTEM_0_gen.*";
				select ".sdata.OS_SYSTEM_0_gen.*";
			}
		}
		"MK_RSA_OS_SYSTEM_0" = "_lc_ub_data_C0.OS_SYSTEM_0";

		/*
		 * Output section bss_C0.OS_SYSTEM_0 (Type BSS)
		*/
		group (align=64, nocopy)
		{
			section "bss_C0.OS_SYSTEM_0" (attributes=rw, blocksize=32)
			{
				select ".bss.OS_SYSTEM_0_gen.*";
				select ".zbss.OS_SYSTEM_0_gen.*";
				select ".sbss.OS_SYSTEM_0_gen.*";
				select ".lbss.OS_SYSTEM_0_gen.*";
			}
		}
		"MK_BSA_OS_SYSTEM_0" = "_lc_ub_bss_C0.OS_SYSTEM_0";
		"MK_RLA_OS_SYSTEM_0" = "_lc_ue_bss_C0.OS_SYSTEM_0";

		"IOC_RSA_READABLE_OS_SYSTEM_0" = "BOARD_C0_RAM_BEG";
		"IOC_RLA_READABLE_OS_SYSTEM_0" = "BOARD_C0_URAM_END";

	}
	
	group (contiguous, ordered, load_addr = mem:int_rom)
	{
		group (align=64)
		{
			section "initdata.data_C0.App1" (fill=0, attributes=r, blocksize=64)
			{
				select "\[.data.App1_gen.*\]";
				select "\[.zdata.App1_gen.*\]";
				select "\[.sdata.App1_gen.*\]";
				select "\[.data.demo.*\]";
				select "\[.zdata.demo.*\]";
				select "\[.sdata.demo.*\]";
			}
		}
		"MK_RDA_App1" = "_lc_ub_initdata.data_C0.App1";

		group (align=64)
		{
			section "initdata.data_C0.OS_SYSTEM_0" (fill=0, attributes=r, blocksize=64)
			{
				select "\[.data.OS_SYSTEM_0_gen.*\]";
				select "\[.zdata.OS_SYSTEM_0_gen.*\]";
				select "\[.sdata.OS_SYSTEM_0_gen.*\]";
			}
		}
		"MK_RDA_OS_SYSTEM_0" = "_lc_ub_initdata.data_C0.OS_SYSTEM_0";

	}
	/*
	 * -----------------------------------------------------
	 * Anonymous catch-all sections for everything remaining
	 * -----------------------------------------------------
	*/
	
	group (contiguous, ordered, run_addr = mem:int_ram_core0)
	{
		/*
		 * Output section data.anon (Type DATA)
		*/
		group (align=64)
		{
			section "data.anon" (attributes=rw, blocksize=64)
			{
				select ".data";
				select ".data.*";
				select ".zdata";
				select ".zdata.*";
				select ".sdata";
				select ".sdata.*";
			}
		}
		"MK_ANON_DATA" = "_lc_ub_data.anon";
		"MK_ANON_DATA_END" = "_lc_ue_data.anon";

		/*
		 * Output section bss.anon (Type BSS)
		*/
		group (align=64, nocopy)
		{
			section "bss.anon" (attributes=rw, blocksize=32)
			{
				select ".bss";
				select ".bss.*";
				select ".zbss";
				select ".zbss.*";
				select ".sbss";
				select ".sbss.*";
				select ".lbss";
				select ".lbss.*";
			}
		}
		"MK_ANON_BSS" = "_lc_ub_bss.anon";
		"MK_ANON_BSS_END" = "_lc_ue_bss.anon";

	}
	
	group (contiguous, ordered, load_addr = mem:int_rom)
	{
		group (align=64)
		{
			section "initdata.data.anon" (fill=0, attributes=r, blocksize=64)
			{
				select "\[.data\]";
				select "\[.data.*\]";
				select "\[.zdata\]";
				select "\[.zdata.*\]";
				select "\[.sdata\]";
				select "\[.sdata.*\]";
			}
		}
		"MK_ANON_IDAT" = "_lc_ub_initdata.data.anon";

	}
}