I am trying to implement a "post build step" in my Aurix Project.  Anything I put in the Post Build Steps Command, fails when I re-build my project.  Pre-Build Steps work fine.  The error I get is: "XCP/AurixCAN.d:5: *** target pattern contains no '%'. Stop.".  I am running version 1.5.2 of Aurix Development Studio.  The post-build step appears to be written to the Make file correctly.  Any Ideas or workarounds??

BTW: BuildA2L works just fine from the command line.

Hello, good morning.
I got some doubts regarding the S70FL01GSAGMFI010 flash memory
As it works with SPI, I would like to know if it is possible to use the same protocol usually used with SD cards (SPI+FAT file system).
Thanks in advance, Luis Felipe.

Hello everyone,
I have TOM generating PWM output and ADC.
How can I disable the ADC conversion for the duration of the PWM switch.

Thanks in advance.

Hi Team,

I am setting trap enable for McuCPU0ESR0TrapEnable in MCAL. i.e. enabling trap on ESR0 pin. When trap is set using TRAPSET[ESR0T] bit then it should jump to some trap location. But it is not jumping to any trap location. It working normally. Please correct me if I am wrong.

Please let me how can I use this trap? 

ESR0 trap is enabled in TRAPDIS0 register. 

Thanks in advance.

Sagar

Hey all,

I'm looking into interfacing a PSoC5LP to a bit of a strange I2C Master.  Rather than being designed to run on a bus, I have to interface using SDA/SCL and an INT pin in a "point to point" configuration.  The idea is easy enough, it gives a edge on the INT line, I catch it with the PSoC, and read the 9 data bytes that it sends, but there's a twist. 

The catch is this device does not send an address, just the raw data bytes.  How can I adjust the SI2C to account for this?  I see I can use either Software/Hardware address decoding.  Hardware is probably out of the question since there's just no address at all.

This leaves me with software decoding, in which case it seems like modifying the ISR in SI2C_INT.c to just drop bytes immediately into the buffer rather than doing a check on the address might work.  Maybe some custom code placed in the SI2C_SW_ADDR_COMPARE_interruptStart code block in the ISR?  I could maybe set the "expected address" to something that should never occur as the first byte received (would need to see if this is possible, it only has 1 bit of data, the rest are "Reserved", so maybe they'll read all 0?  That would make it easy.) so it will drop into the address compare where I can drop my custom code to place the data in the receive buffer rather than use it as an address?

An easier option after looking further may be just to use the SI2C_ISR_EntryCallback(); and have it perform essentially a modified version of the stock Slave I2C code.

I'd be interested if anyone out there had any better options, maybe even something that just works in hardware?

Thanks!

Hi,

I am using Tc37x.

I want my SMU to track MTU alarms all the time. For that I have written the code something like this

  IfxMtu_enableModule();

clear_MTU_MBIST_Errors(IfxMtu_MbistSel mbistSel);

 

Basically, just enabled the MTU clock and then clear the errors caused due to system reset.

Now which other functions should I write [ from IfxMtu.h] to continuosly track the MTU errors.

 

 

I have a few questions:

1] for DAM0 do I need to enable DAM0 module too? [by enabling DAM0_CLC?]

2] If I get any MTU error, will my corresponding smu alarms get set automatically? [ As i need to check if smu alarms are set or not, does it happen auto? or do i have to set "AlarmStatus" after configuring MTU bits?]

3] I can see that FSI_RAM is not used in the enum. So do how should I disable this alarm after system reset?

 

4] I want to set an alarm status in smu (say alm0[9-11]) and lets say I choose  mbistSel =  IfxMtu_MbistSel_cpu0Dspr.

How to set this MTU alarm ? and the corresponding SMU alarm?

 

5] and for DMA/gigethernet 

 

I cleared the mbist 41[DMA] and 82,83[ethermacRx/Tx]. But the smu alarm doesn't set to "low", its still "high".

 

 

Thank you!!

 

error occurring in KEIL IDE which weren't shown when executed in PSOC creator. Not able to resolve the error either. attached is the image of the problem I am facing.  please let me know where is this going wrong.

thanks 

Hello,

using Device configurator and QSPI configurator how could i generate a flashloader for Modbustoolbox of external memory?

does the .c/.h file generated used by the tool or does it generates a .elf file to be downloaded in RAM the case in IAR and MDK-ARM?

Thanks in advance.

Hi all,

I am trying to confirm SRAM ECC enabled or disabled status by reading SRAM related ECCS register value. Under LAUTERBACH TRACE32 environment, after execution of code in Figure 1, below steps are manually operated.

Figure 1 Enable MTU module

1. Press Pause in TRACE. MTU_MEMTEST0.CPU0PTEN set Enable, press Run;

2. Press Pause, no Trap found.  MTU_MEMTEST0.CPU0PSEN, press Run;

3. MTU_MEMTEST0.CPU1PTEN set Enable and no Trap;

5. MTU_MEMTEST0.CPU1PSEN set Enable and no Trap;

6. MTU_MEMTEST0.CPU1DTEN set Enable and no Trap;

7. MTU_MEMTEST0.CPU1DSEN set Enable and no Trap;

8. MTU_MEMTEST0.CPU0DSEN set Enable and Enter Context Management Trap is found after Run and Pause;

I'm curious about the reason why the operation of setting CPU0DSEN leading to Trap. Then, I think there should be a right approach of enable CPU0DSEN.

Hope somebody share suggestion with me. Thanks very much !

Best Regards,

tripod