Hi All, we are a start-up with a renewable product and have designed around the above chip. Unfortunately with all the supply upheaval we can't find any of these chips for our first production run. If anybody can help or knows where we can get 20 or even 10No. I would be very grateful. Thanks, Kieran

Hi,

For my initial evaluation of USB3 Vision, I am using the source code shared in the forum. Using that source code, I am able to enumerate the device as a USB3 Vision device, but I cannot connect to any GenICAM application to test the streaming. Any guidance on this would be appreciated.

Thanks in Advance,

Vigneshkumar R.

Hello,

I am trying to understand the JTAG locking / unlocking mechanism in CYT2B9, till now I have gathered the below information 

JTAG locking can be done when we are either in life cycle state NORMAL or SECURE

When we are in life cycle state Normal, we can configure SFLASH area(0x1700_1A00) to enable authenticated debug access, to write into SFLASH area we need to use Write-Row system call

When we are in life cycle state Secure, we can configure EFUSE bits to enable authenticated debug access, to write into EFUSE bits we need to use Transition to Secure system call

Both SFLASH/EFUSE bits are having similar structure, details of each bit can be found in the below snippets

SFLASH area

 

 

EFUSE bits

 

 

To enable authenticated debugging we need to set AP_CTL_xxx_DISABLE to “01” and SYS_AP_MPU_ENABLE to “0” either in SFLASH or EFUSE based upon life cycle state. Boot will make CPUSS_AP_CTL.SYS_DISABLE and CPUSS_AP_CTL.SYS_ENABLE to 0 disabling debugging access and will not configure SYS_AP_MPU.

To unlock JTAG we need to implement our own authentication logic and once successfully authenticated we can set CPUSS_AP_CTL.xx_ENABLE to “1“ to gain debugging access.

 

 

 

I have the below queries

1. As per TRM, debug access restrictions can be enabled and disabled in SFLASH area in NORMAL mode but in FAQ document it says once debug access is disabled, it cannot be enabled, see the below snippets for more information

            TRM  

          FAQ

   Whether SFLASH area is OTP or not?

2. Inter-processor communication (IPC) is one of the method to communicate the password to the HSM. For example, SYS_AP_MPU is enabled with limited access to only specific MMIO for IPC register, and minimal RAM to initiate IPC interrupt on HSM. After receiving the password, HSM validates it and, if correct, reconfigures SYS_AP_MPU to allow access for debugging

As per the above statement from FAQ, I understand that to provide the password to CM0+ core we need to use IPC mechanism, what is SYS_AP_MPU? as i didn’t found any information about it in TRM and what’s the purpose and usage of it during JTAG unlocking

3. What's the advantage of moving life cycle state "SECURE" if authenticated debug can be achieved in NORMAL state?

4. Write-Row API returns an error status when called during an active embedded operation? so when exactly we need to call this API i.e. during initialization or by checking any register status

 

Hi cypress,

I am using CCG3PA as a sink for implementing  QC 3.0 functionalities where when I use QC 4.0+  which are backward compatible it is automatically starting PD Contract. I need to stop PD contract from happening and in the same time time i need  Rd pull up functionalities to achieve QC 3.0 functionalities.  what should I do, how can I Disable PD communication and have Type c capabilities.

Regards

@BhargavGolla

我使用的开发板是CYUSB3KIT-003。开发板在StreamerExample模式下正常启动后，PC端通过EP0端口给开发板发送一个字节，开发板响应代码如下所示：

    if(itype == 64 && itarget == 2 && ireq_type==66 && irequest == 11)
    {
        CyU3PDebugPrint(6, "switch to bootloader\r\n");
        CyU3PUsbAckSetup ();
        CyU3PThreadSleep (10);
        app_stop();
        CyU3PDebugDeInit ();
        CyU3PUartDeInit ();
        //CyU3PConnectState(CyFalse, CyFalse);
        CyU3PUsbSetBooterSwitch (CyTrue);
        CyU3PUsbJumpBackToBooter (0x40078000);
        //CyU3PDeviceReset(CyTrue);
        while (1)
            CyU3PThreadSleep (100);
        bis_handled = CyTrue;
    }

 我希望它切换到bootloader模式，结果设备不见了，如下图所示：

怎样用代码从StreamerExample模式切换到bootloader模式呢？如下图所示：

Hi.

I'm trying to use the HAL System Power Management library to put the CM4 to sleep. So far, I've had no luck, and as I have found too many times, there is very little documentation available, and no examples. What documentation exists (e.g. Architecture TRM) is unclear, even suggesting that only masked interrupts can wake up a sleeping CPU.

Here's the environment:

• PSoC 63 with BLE in a custom board.
  • MTB 2.3.0 
  • BSP 2.3.0
  • PDL 2.3.0
  • HAL 2.1.0
• CM4 and CM0+ running FreeRTOS
• Several peripherals in use (BLE, I2C, UART, SPI, RTC, TWPCM, etc.)

1. I registered four callbacks using cyhal_syspm_register_callback(). 
2. I call cyhal_syspm_sleep().
3. The four callbacks are called with state set to CYHAL_SYSPM_CB_CPU_SLEEP and mode set to CYHAL_SYSPM_CHECK_READY. All callbacks return true.
4. The four callbacks are called again with state set to CYHAL_SYSPM_CB_CPU_SLEEP, but this time mode set to CYHAL_SYSPM_BEFORE_TRANSITION.
5. The four callbacks are immediately called a third time with state set to CYHAL_SYSPM_CB_CPU_SLEEP, but this time mode set to CYHAL_SYSPM_AFTER_TRANSITION.

The first problem is that the CPU either doesn't sleep, or wakes up immediately. I disable the RTOS SysTick interrupt in one of the callbacks. I also disable several other peripheral interrupts, and turn off the BLE stack, none of which has made a difference. It's likely that some interrupt is firing, but I can't think of a good way to determine which is the culprit.

The second problem is that the stated behavior, namely that the callbacks are called on wakeup (CYHAL_SYSPM_AFTER_TRANSITION) in the reverse of the order in which they are called on sleep (CYHAL_SYSPM_CB_CPU_SLEEP) does not match the observed behavior.
Callbacks are always called in the same order, even when one of the callbacks returns false in response to CYHAL_SYSPM_CHECK_READY.

Has anyone successfully used cyhal_syspm_sleep() to put one of the CPUs to sleep?

Thanks,

-Nick

如附件 是modus2.4操作QSPI的工程，gImage_2_2[20]这个数组没有烧录到外部flash中，读取的数据是外部flash原来的数据。 同样的代码modus2.2就操作正常，请大神帮我看下是什么问题，已经折腾我三天了。这个代码以前也是赛普拉斯AE帮我搞的，现在为了方便开发，需要移植到modus2.4上面。