Good morning, I am currently working on the development of a product which includes CY62157EV30LL-45ZXA SRAM.

We are using the device in 8-bit data mode, using address pins A0-A19, with BHE and BLE tied high, and BYTE tied low.
In many areas of the datasheet, it is specified that '29. During this period, the I/Os are in output state. Do not apply input signals.'

We understand this that if the I/Os are in an output state, and we drive a voltage into these pins at this time - it is possible that we may physically damage the memory. We are not comfortable shipping a product that could be damaged by firmware - validated firmware or not.

Are we understanding this correctly? And in such a case, would Infineon recommend the use of series resistors on the data lines to stay within the 20mA 'output current into outputs (LOW)' specification, within the maximum ratings section of the datasheet?

Many thanks in advance

Hi,

on my CYT4BF device i have an Autosar Application running only on CM7 core. For Bootcore CM0+ there is no application available. How do i manage the correct startup and "running" behaviour for the CM0+ core?

Thanks,

Martin

Hello,

I have one question regarding the crystal placement.

Can someone please check our current crystal placement? Is it advisable to place the load capacitors near to the crystal pins or near to the IC? Kindly review the screenshot for our current placement and advise.

Also as per Infineon checklist, it is recommended to use crystal having drive current of around 600uW but in 4-SMD package we are not able to find the desired part. We are only able to get maximum of 300uW, so we added a series resistor for current limiting. Is it a right way? Also which one is better to use with this IC, Crystal or Oscillator?

 Thanks in advance

Hi,

What is the meaning of table type of pages 0,1,2.. etc in Config mode Get status? Section 3.4 & Table 23, Page No 23

Device Programming

Thanks

Mathan

Hi

I'd like to kwow what is the proper solution to start syncronously the conversion  of two ADC channels queue. Lets suppose I've on G8 and G9 two queue of 10 elements (from CH0 to CH9 to make it simple).  And I want to start the conversion of these two chains syncronously.. how can I do?

If I set the two queue and combine the two CH0 and master/slave I see that only G8 (the master) continue the conversion to the other channels  but G9 convert only the CH0.

Another solution is to use the same trigger signal for both the group and this seems to work... but what is the difference between the two approach?

Thanks in advance

Hi All,

i tried to implement RTos into Tc212 LIbrary which i have done before with the TC387 Board.but for TC212 family i am getting error as below .

16:02:52 **** Incremental Build of configuration Debug for project BmsSwRTos ****
make --output-sync -j8 all
Building target: BmsSwRTos.elf
TASKING VX-toolset for AURIX Development Studio (non-commercial): control program v1.1r8 Build 22011964
ltc E112: cannot locate 60 section(s):
ltc I455: requirement: 32K (0x82d9) bytes of RAM area in space mpe:vtc:linear
ltc I456: section type: range restriction - range(s) 0x70000000-0x7000c000
ltc I456: section type: group restriction - contiguous
ltc I457: .data.Cpu0_Main.g_cpuSyncEvent (5984) (0x4 bytes)
ltc I457: .data.IfxPort_PinMap.IfxPort_P00_0 (3052) (0x8 bytes)
ltc I457: .data.IfxPort_PinMap.IfxPort_P02_6 (3069) (0x8 bytes)
ltc I457: .data.IfxPort_PinMap.IfxPort_P02_7 (3070) (0x8 bytes)
ltc I457: .data.IfxPort_PinMap.IfxPort_P02_8 (3071) (0x8 bytes)
Invoking: TASKING Linker
ltc I457: .data.IfxPort_PinMap.IfxPort_P11_11 (3078) (0x8 bytes)
cctc -lrt -lfp_fpu -lcs_fpu -Wl-Oc -Wl-OL -Wl-Ot -Wl-Ox -Wl-Oy -Wl--map-file="BmsSwRTos.map" -Wl-mc -Wl-mf -Wl-mi -Wl-mk -Wl-ml -Wl-mm -Wl-md -Wl-mr -Wl-mu --no-warnings= -Wl--error-limit=42 --exceptions --strict --anachronisms --force-c++ -Ctc21x -o"BmsSwRTos.elf" -Wl-o"BmsSwRTos.hex:IHEX" --lsl-core=vtc --lsl-file=../Lcf_Tasking_Tricore_Tc.lsl ./OS/FreeRTOS/portable/TriCore/port.o ./OS/FreeRTOS/portable/MemMang/heap_4.o ./OS/FreeRTOS/croutine.o ./OS/FreeRTOS/event_groups.o ./OS/FreeRTOS/list.o ./OS/FreeRTOS/queue.o ./OS/FreeRTOS/stream_buffer.o ./OS/FreeRTOS/tasks.o ./OS/FreeRTOS/timers.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxAsclin_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxCcu6_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxGpt12_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxGtm_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxMultican_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxPort_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxQspi_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxScu_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxSent_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxSmu_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_PinMap/IfxVadc_PinMap.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxAsclin_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxCcu6_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxCpu_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxDma_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxFlash_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxGtm_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxMtu_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxMultican_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxPort_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxQspi_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxScu_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxSent_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxSmu_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxSrc_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxStm_cfg.o ./Libraries/iLLD/TC22A/Tricore/_Impl/IfxVadc_cfg.o ./Libraries/iLLD/TC22A/Tricore/Stm/Std/IfxStm.o ./Libraries/iLLD/TC22A/Tricore/Src/Std/IfxSrc.o ./Libraries/iLLD/TC22A/Tricore/Scu/Std/IfxScuCcu.o ./Libraries/iLLD/TC22A/Tricore/Scu/Std/IfxScuEru.o ./Libraries/iLLD/TC22A/Tricore/Scu/Std/IfxScuWdt.o ./Libraries/iLLD/TC22A/Tricore/Port/Std/IfxPort.o ./Libraries/iLLD/TC22A/Tricore/Port/Io/IfxPort_Io.o ./Libraries/iLLD/TC22A/Tricore/Gtm/Std/IfxGtm.o ./Libraries/iLLD/TC22A/Tricore/Gtm/Std/IfxGtm_Cmu.o ./Libraries/iLLD/TC22A/Tricore/Gtm/Std/IfxGtm_Dpll.o ./Libraries/iLLD/TC22A/Tricore/Gtm/Std/IfxGtm_Tbu.o ./Libraries/iLLD/TC22A/Tricore/Gtm/Std/IfxGtm_Tim.o ./Libraries/iLLD/TC22A/Tricore/Gtm/Std/IfxGtm_Tom.o ./Libraries/iLLD/TC22A/Tricore/Cpu/Trap/IfxCpu_Trap.o ./Libraries/iLLD/TC22A/Tricore/Cpu/Std/IfxCpu.o ./Libraries/iLLD/TC22A/Tricore/Cpu/CStart/IfxCpu_CStart0.o ./Libraries/Service/CpuGeneric/SysSe/Bsp/Assert.o ./Libraries/Service/CpuGeneric/SysSe/Bsp/Bsp.o ./Libraries/Infra/Platform/Tricore/Compilers/CompilerDcc.o ./Libraries/Infra/Platform/Tricore/Compilers/CompilerGhs.o ./Libraries/Infra/Platform/Tricore/Compilers/CompilerGnuc.o ./Libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.o ./Libraries/aurix_pin_mappings.o ./Configurations/Debug/sync_on_halt.o ./AppSw/OsTasks/OsTasks.o ./AppSw/Led/Leds.o ./ASW/WakeupAndPowerManagement/source/WakeupAndPowerManagement.o ./ASW/WakeupAndPowerManagement/config/WakeupAndPowerManagement_Cfg.o ./ASW/VcuCommunication/source/VcuCommunication.o ./ASW/VcuCommunication/config/VcuCommunication_Cfg.o ./ASW/VAndISynchronization/source/VAndISynchronization.o ./ASW/VAndISynchronization/config/VAndISynchronization_Cfg.o ./ASW/Soh/source/Soh.o ./ASW/Soh/config/Soh_Cfg.o ./ASW/Soc/source/Soc.o ./ASW/Soc/config/Soc_Cfg.o ./ASW/Rtc/source/Rtc.o ./ASW/Rtc/config/Rtc_Cfg.o ./ASW/PowerPrediction/source/PowerPrediction.o ./ASW/PowerPrediction/config/PowerPrediction_Cfg.o ./ASW/NvmManagement/source/NvmManagement.o ./ASW/NvmManagement/config/NvmManagement_Cfg.o ./ASW/KLMonitoring/source/KLMonitoring.o ./ASW/KLMonitoring/config/KLMonitoring_Cfg.o ./ASW/FaultAndSafeStateControl/source/FaultAndSafeStateControl.o ./ASW/FaultAndSafeStateControl/config/FaultAndSafeStateControl_Cfg.o ./ASW/FanControl/source/FanControl.o ./ASW/FanControl/config/FanControl_Cfg.o ./ASW/CurrentSensing/source/CurrentSensing.o ./ASW/CurrentSensing/config/CurrentSensing_Cfg.o ./ASW/ChargingController/source/ChargingController.o ./ASW/ChargingController/config/ChargingController_Cfg.o ./ASW/CellDataAcquisition/source/CellDataAcquisition.o ./ASW/CellDataAcquisition/config/CellDataAcquisition_Cfg.o ./ASW/CellBalancing/source/CellBalancing.o ./ASW/CellBalancing/config/CellBalancing_Cfg.o ./ASW/BatteryDisconnect/source/BatteryDisconnect.o ./ASW/BatteryDisconnect/config/BatteryDisconnect_Cfg.o ./Cpu0_Main.o
ltc I457: .data.IfxPort_PinMap.IfxPort_P11_12 (3079) (0x8 bytes)
ltc I457: .data.IfxPort_PinMap.IfxPort_P11_2 (3080) (0x8 bytes)
ltc I457: .data.IfxPort_PinMap.IfxPort_P15_0 (3098) (0x8 bytes)
ltc I457: .data.IfxPort_PinMap.IfxPort_P20_8 (3116) (0x8 bytes)
ltc I453: ... (50 more I457 messages suppressed)
make: *** [makefile:115: BmsSwRTos.elf] Error 1
"make --output-sync -j8 all" terminated with exit code 2. Build might be incomplete.

16:02:54 Build Failed. 2 errors, 0 warnings. (took 1s.883ms)

Kindly help me to solve this and let me know this TC212 controller supports RTos  OS or not.

Many Thanks,

Krishnayya

I designed a USB test module using CYUSB3014. This USB test module is used to test the USB HUB. The module runs the cyfxbulksrcsink example, and the circuit design completely refers to CYUSB3KIT-003.

I simulated some open-circuit and short-circuit faults of the superspeed signal on the USB HUB side, and then verified whether these faults can be detected by the CYUSB3014 module, and found that the following three fault tests failed:

1. SSRX_N open: Enumeration and data communication are completely normal.
2. SSTX_P shorted to GND: Enumeration and data communication are completely normal.
3. SSTX_N shorted to GND: Enumeration and data communication are completely normal.
4. SSRX_P shorted to GND: Enumeration and data communication are completely normal.
5. SSRX_N shorted to GND: Enumeration and data communication are completely normal.

What's the problem?

Is it possible to modify the firmware to solve all or some of the above problems?

If it can't be solved by modifying the firmware, what hardware circuit can solve the above problems, I hope to get your suggestions.