Hi all,

The RBSOA(reverse bias safe operating area) is written on the data sheet.
Could you please show me the SCSOA(Short circuit safe operating area) both at 25 degrees and 150 degrees, if you have?

Also, could you please show me the maximum allowable loss value at short circuit, if you have?

Best regards,

MS

I'm using CAN transceiver TLE9255 and trying to create a small test code that can trigger Can Transceiver to Sleep WUP Sub-Mode then wake up by pattern. 

After setting up the configuration followed by chapter 5.4.1 in the datasheet, I trigger it to sleep mode then observe the INH pin and read the operation mode to verify its behavior.

I observe that the INH pin is low after I trigger sleep mode, but the operation mode get from the register is the normal mode. 

Only the sleep mode can drive the INH pin to 0, so I'm pretty sure that the Can transceiver was in sleep mode. So my concern is can we read the actual operation mode when the CAN transceiver is in sleep mode?

いつもお世話になっております。

IPLK60R360PFD7のデータシート7ページに記載している

Max. transient thermal impedanceの近似式を提供して頂くことは可能でしょうか？

PLK60R360PFD7

↓

https://www.infineon.com/dgdl/Infineon-IPLK60R360PFD7-DataSheet-v02_00-EN.pdf?fileId=5546d4626fc1ce0...

以上、よろしくお願いいたします。

Hi all!

Is it possible to run GPIF Designer under Linux in any way?

Currently I have troubles to run it via wine and mono.

According to TRAVEO™ T2G Automotive Body Controller Entry Family Architecture Technical Reference Manual (TRM) 20.6 Debug Mode, Table 20-5. Debug Modes: When configure DEBUG_RUN to 0 and DEBUG_TRIGGER_ENABLE to 1, watchdog counter is stopped only when a debugger is connected and the CPU is halted during a breakpoint.

However, the watchdog counter does not stop when a debugger is connected and the CPU is halted during a breakpoint.

It seems that to pause at a breakpoint while debugging, need configure the trigger matrix to connect the related CPU halted signal to the trigger input for the related watchdog timer:

Could you kindly help to share how to configure the trigger matrix to connect the related CPU halted signal to the trigger input for the related watchdog timer?

Thanks very much!

Hi.,i use the j-link to debug the FX3,but it can not enter the CyU3PKernelEntry ();How can i debug enter the thread_enter function?

你好，上面是我模仿an58764设计的CDC系统，我已经能正常通信。但是我仍然有一个问题没有解决，请帮忙解答，谢谢。

以前在这里提问过了，但是可能因为语言表达问题，没办法把自己的问题说清楚，以至于没有得到满意的答复。

https://community.infineon.com/t5/USB-low-full-high-speed/About-CDC-and-endpoint/m-p/325304#M10106

问题:

 我从8051发了数据到PC，在EP6IN看到的数据是对的，但是我在PC看到的是ffffffff... ； 我重新从8051再发一次相同数据到PC后，EP6IN和PC的数据就都是对的了，也就是说我需要发两次请求才可以得到想要的数据。于是我就想了一个方法，第一次先arm一个不使用的EP（比如EP2IN）,再arm真实需要的EP6IN就可以在PC只得到想要的数据了（不会有第一次的ffffff数据）。能帮忙分析一下是因为什么问题吗？如果可以的话麻烦留个邮件地址以便及时和您沟通，谢谢。

Hello,

I followed AN75779 to implement an 8 bit interface UVC. I have a card with a fx3 and a fpga. With fpga, I generate signals lv, fv and pixels (1920 * 2 * 1080 /  Y = counter;  U / V = 0x80). Everything works and I have a grey-scale image. But when I want to switch to 16-bit interface, it does not work. However, I modified the GPIF with a 16-bit bus and a limit of 8183 meter. Obviously, the state machine is stuck in a state PARTIAL/FULL_BUFF_IN_SC0/1. Any idea?

Thank you!