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We are using CYW920721 in our project and our application is based out of the example code Audio watch.
Connection initiator side BD address:8e 6d 17 42 c5 2c
Peer side BD address: a6 4b 12 42 6e 2c
BD address correption:
We are seeing wired issue when the connection is initiated with some BD address, connection call back from the stack result in first bytes corrupted sometimes results in pairing failure.
Connection initiator side log
[2023-05-25 09:04:04.205] hci_control_handle_bond:wiced_bt_connect a6 4b 12 42 6e 2c
[2023-05-25 09:04:04.684] wiced_bt_start_authentication(CALLED):result=1
[2023-05-25 09:04:04.731] hci_connection_status_change_callback handle:000b ac:46:12:42:6e:2c isConn=1, handle=000b, reason=0, transport=1 cnt{conn=1|notConn=0}
[2023-05-25 09:04:04.731] btm_event_handler 0x13
Pairing failures with status 5:
Also, the device retries connection to the same address that time call back has the right address but pairing complete with status 5 means pairing not allowed whereas remote devices pairing is configured to be allowed.
Peer side log
[2023-05-25 09:03:53.103] hci_control_ag_init:pcmCfg mode=0 role=1 lsbFirst=0 fillBits=0 fillData=0 fillNum=3 rightJustify=0 frame_type=0
[2023-05-25 09:03:53.103] + hci_control_proc_rx_cmd
[2023-05-25 09:03:53.103] cmd_opcode 0x03
[2023-05-25 09:03:53.103] + hci_control_proc_rx_cmd
[2023-05-25 09:03:53.103] cmd_opcode 0x08
[2023-05-25 09:03:53.145] + hci_control_proc_rx_cmd
[2023-05-25 09:03:53.145] cmd_opcode 0x09
[2023-05-25 09:03:53.145] Set the pairing allowed to 1
[2023-05-25 09:03:53.145] + hci_control_proc_rx_cmd
[2023-05-25 09:03:53.145] cmd_opcode 0x0f
[2023-05-25 09:03:53.145] Local Bluetooth Address: [a6 4b 12 42 6e 2c ]
---
Connection initiator
[2023-05-25 09:04:40.554] hci_control_handle_bond:wiced_bt_connect a6 4b 12 42 6e 2c
[2023-05-25 09:04:41.143] wiced_bt_start_authentication(CALLED):result=1
[2023-05-25 09:04:41.143] hci_connection_status_change_callback handle:000b a6:4b:12:42:6e:2c isConn=1, handle=000b, reason=0, transport=1 cnt{conn=1|notConn=0}
[2023-05-25 09:04:41.143] btm_event_handler 0x13
[2023-05-25 09:04:41.143] BTM_PAIRED_DEVICE_LINK_KEYS_REQUEST_EVT: find device a6 4b 12 42 6e 2c
[2023-05-25 09:04:41.143] Key retrieval failure
[2023-05-25 09:04:41.143] btm_event_handler 0x08
[2023-05-25 09:04:41.143] BTM_PAIRING_IO_CAPABILITIES_BR_EDR_REQUEST_EVT bda a6 4b 12 42 6e 2c
[2023-05-25 09:04:59.107] btm_event_handler 0x0b
[2023-05-25 09:04:59.107] BTM_PAIRING_COMPLETE_EVT
[2023-05-25 09:04:59.107] pairing complete evt: a6 4b 12 42 6e 2c as 2c 6e 42 12 4b a6 status 5
After few retries device pairs successfully. Kindly share your thought. I wanted to raise this as high priority issue because it affects our connection cycle.
Show LessThe answer posted on the following support ticket is clearly incorrect for CYUSB3035 hardware documentation, though it may be true for the GPIF II Designer development SW. From:
EZ-USB® FX3™ Technical Reference Manual
4.1 GPIO Pins:
All 60 GPIO pins in FX3 can function as GPIOs. ...
Table 4-1 lists CLK or PLK as an alternate function (not primary) for GPIO16.
Page 241, 10.4.2 GCTL_GPIO_SIMPLE lists bit position 16 as controllable, R/W.
Page 243, 10.4.3 GCTL_GPIO_COMPLEX also lists bit position 16 as controllable, R/W.
Can GPIO_16 be configured as GPIF-II Output on CYUSB3035?
So how do you write and implement micro code for the FX3 state machine with having to be handcuffed by GPIF II Designer?
Where is the micro code definition document to tell you how to do that?
Show Less
I use the cyusb3kit-003 to connect FPGA with the fifoslave mode,I use the code that can be used in other people ,but I found that flag_a and flag_b is used to write data to cyusb3kit, they are useful,but the flag_c and flag_d is used to read data from cyusb3kit , they seems like not working, when i select the botton that Transfer Data-OUT ,i found that flag_c and flag_d was always be low, i also set the water maket, but they never change, they are in low forever,and then i Transfer Data-IN ,the writing process was broken too. I can't found the reason that flag_c and flag_d change to low and keep this forever.
Show LessHi,
I have downloaded application note for AN75779 image sensor configuration with FX3 board, in document it is mentioned a prebuild image file is present in the zip file but I am not able to find the image file. Can you please send me latest application note or zip file for AN75779 which has image file or any way I can generate the image file.
Thank You!!
Show LessHi,
I am using CYBT-343026 Evaluation Board. My goal is to transfer data from MCU to remote peer over BLE. First, to verify proper communication I connect and start communicating using PC serial terminal through PUART with flow control disabled. After that, to check flow control works properly I enable Flow Control of module using API command and set RTS pin of Host (which is connected CTS of module) HIGH through PC serial terminal and I send some command to module and expect that I will not get any response because as CTS input pin of Module is HIGH, module should not transmit data, but still module is transmitting.
I am using below pins to observe signals.
What could be the reason of this behavior?
Regards,
Harshvardhan
Show LessI write a fw for FX3 application.
But after programming firmware, the program menu of device is only show FX2 and disable FX3.
Meanwhile, I write a C# program to detect my firmware found device object will be asserted, because dev object will be set to null when I cast device to CyFx3Device(dev = usbDevices[DeviceName] as CyFX3Device).
I tried to copy Device Descriptor of SDK example UsbSpiDma, and my firmware is still recognized as FX3 Device.
Can anyone give suggestions to me, please?
Show Less
Dear supporter
I want to translate the following KBA, please confirm to my work.
Best Regards.
YuMa
Show Less我用的芯片是psoc6,基于psoc creator4.4,基于CE217633这个示例,在M4 的main函数加入NVIC SystemReset(), 实现系统每隔5秒重新启动,但系统有10%的概率会挂死。添加的代码如下:
int main()
{
UART_START();
printf("reset\r\n\r\n");
Cy_SysLib_Delay(5000);
NVIC_SystemReset();
.....
}
请问 NVIC_SystemReset() 这样用不安全吗?
Show LessSheetHello
Regarding the following description of 1.4 I/O subsystem on Page 6 of the CCG3PA Data-Sheet
The GPIO block implements the following:
>Seven drive strength modes:
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
(Q1)Could you tell us about the "Resistance value" for each of the above weak pull-up and strong pull-up?
Regarding the following description "3 Pinouts" on Page8 of the CCG3PA Data-Sheet.
>4. AXRES pin will be internally pulled up during the Power On I/O initialization >time (See Table 7 for more details)
(Q2) Above, the AXRES pin is described as an initial pull-up, but is it a weak pull-up or a strong pull-up?
Best Reards
Show Less