Hi, I am wondering how to transition a design from the PSoC 5LP to the PSoC 3 with the minimal amount of changes possible (not having to redesign the hardware and software). I am wondering if there are any notable changes I must be aware of besides the specs difference. Of course, a simple change of device and copy and paste will not build or compile successfully. Any helpful information will suffice. The reason I am downgrading to an older chip is because there is a massive chip shortage with a year lead time on a 5LP chip that is currently being used in the design.

Hi,

In TC3xx usermanual, it's said that all-0 and all-1 will be read with ECC errors. Does it mean a const array with 8 bytes consecutive 0xFF can't be read witout ECC error?

Best regards

Jamber

My company has two of the EZ-PD CY4500 analyzers.  I successfully installed the analyzer software on my PC and got it working with no problems.  I'm assisting one of our technicians with installing it on his computer.  He downloaded and installed the EZ-PD Utility  and the latest Analyzer.  When he ran the Analyzer software, it said he needed to update the firmware.  When he ran the firmware update tool, it said the device could not be found.

I've found multiple posts on here that say you need to install the Utility to get the drivers, and you need the Analyzer to get the latest software, but none of the posts say if they have to be installed in a certain order or using a particular sequence (like install the Utility, update the firmware, then install the Analyzer, etc.).

The Device Manager shows no driver is associated with the EZ-PD analyzer.  When we tried to update the driver by explicitly pointing at c:\Windows\system32\drivers, it said no compatible driver could be found.  I confirmed that winusb.sys is in that folder.

Both systems are running Win 10 Pro.  The working system has a slightly newer build and different version of winusb.  We are going to try running the Windows update on the non-working system.  If that doesn't work, what else can we try?

Hello Infineon Support,

Apologies, I originally posted about this issue here, but I was taken off the project before I was able to test it out.  I'm back on now and I'm still getting this error after the BLE stack is initialized:

hci_open(): init error (0x4021c00)

The old post wouldn't let me reply so I'm adding some information here.

First off, I can confirm that I have the most up-to-date version of the BSP and libraries available, so that is not the issue.

Second, I'm using the Bluetooth_LE_CapSense_Buttons_and_Slider project as a baseline, and when I run that project, it works as expected and I do not get the HCI error. 

For my project, I copied in the ble_task files and the design.cybt file, so my setup should be the same for all the bluetooth libraries and functions.  I confirmed that my Makefile has the FREERTOS and WICED_BLE components added to it.

There's two other notable differences between my project and the original capsense project:

• My project is a dual core project, with a smaller app running on CM0P
• My project has some WiFi libraries it is using

Could either of those differences cause contention issues with the HCI hardware?  I've tried all sorts of things to get this running but cannot shake this error message.

Best regards,

Cory

Hi! I'm looking at ways to implement "infinite-length" reception for a UART port, where the port receives bytes at a high baudrate for potentially infinite duration.  I can't just use a regular UART app in DAVE set to DMA mode, as this has a limit of 4095 bytes for the longest possible DMA operation.  I did find this post about implementing multi-block DMA transfers, and this seems like it could accomplish what I need if I create a large "ring buffer" of DMA blocks that executes forever.  However, it's only possible to have two multi-block DMA transfers operating at a time, which is a disadvantage for my application, and also this is not implemented in DAVE so I'd have to do a lot of dev work myself.

What I'm wondering is, is it possible to make it so that a "regular" UART DMA is safe to pause and resume?  Looking at the current DAVE UART DMA generated code, it does not use the USIC module's FIFO; it sets the DMA to read the RBUF register directly:

XMC_DMA_CH_SetSourceAddress(ptr_gpdma, ptr_dma_config->dma_channel, (uint32_t)&(handle->channel->RBUF));

This means that if the DMA is stopped, there is only a 2 byte buffer in the USIC, and once those 2 bytes are filled data will be lost.  Therefore, it is not safe to pause the DMA for any significant length of time.  What I'm wondering is, how hard would it be to use the DMA with the RXFIFO?  If we could enable the FIFO, then it would have up to a 32 byte buffer, so you could stop the DMA for longer while you did other stuff. 

I tried to do this in DAVE, but the option to use the FIFO is greyed out while DMA is enabled.  Could one do this in code just by enabling the RXFIFO and changing the DMA to read from OUTR instead of RBUF?  Or is there a deeper reason why RXFIFO plus UART DMA receive is not a supported configuration?  Please let me know if anyone has some insight into this (or if there's a simpler way to do this that I'm missing).  Thanks!

Where does this error come from?

Cannot run program "/JLinkGDBServerCL.exe": Launching failed

Complete error message:

------------------------------------

Error in services launch sequence
Launching command [/JLinkGDBServerCL.exe -if swd -device XMC4700-F144x2048 -endian little -speed 1000 -port 2331 -swoport 2332 -telnetport 2333 -vd -ir -localhostonly 1 -singlerun -strict -timeout 0] failed.
Launching command [/JLinkGDBServerCL.exe -if swd -device XMC4700-F144x2048 -endian little -speed 1000 -port 2331 -swoport 2332 -telnetport 2333 -vd -ir -localhostonly 1 -singlerun -strict -timeout 0] failed.
Cannot run program "/JLinkGDBServerCL.exe": Launching failed

I'm experimenting with the BTS50010-1TAD high side smart switch. However I'm experiencing very scattered values on the current feedback pin. I have connectedb the BTS to a ESP32 MCU.

I also don't understand how the dkILIS vs Rsense is calculated, because the values that is being read is not what I expected. With a 10K Rsense I was expecting 18500 µV per Amp = 18,5 mV per Amp = 0,05 Amp per mV. But what I get is notthis, and with a very inconsistent ratio between Vsense and the actual current measured thru the MOSFET.

Also the Vsense value can easily rise above any commonly available ADC Vmax value, usually 3V3 or 5V. But there is no zener or any other protection circuit recommended in the datasheet for the BTS50010-1TAD. What is the idea here?

This is my circuit:

Results from Vsense measured at IS versus actual mA flowing:

Thank you in advance.