I'm trying to use the backup registers (BREG) on PSOC6/CY8CPROTO-062-4343W to set a value before rebooting.
Documentation on this topic is either elusive, or light.
I started here in section 3.3.5 - https://www.cypress.com/file/385936/download
I found a declaration of a struct BACKUP_V1_Type, which contains 64 bytes of BREG in cyip_backup.h.
There's no detail how to use it tho. Doesn't look like it contains register addresses at all, and just a data structure.
I found a register address for BREG on another PSOC platform in a technical reference manual, but it is not retaining any information when I use CY_SET_REG32 and CY_GET_REG32. Can someone point me to the information? Maybe the TRM for the platform I'm using?
I see that the project creation wizard still does not support the CY8CKIT-064S0S2-4343W board in choosing to create a new project based on BSP selection. You have to go through AWS to get a default project and then modify that in situ.
Can we expect BSP support any time soon? We are nearly at the end of 2021.
For example, the Hello-World blink example:
Only supports the B0S2 version and not the S0S2.
I'm picking up a project and haven't used the Cypress PSOC parts before. I have two board variants with two different PSOC 4 BLE parts in them: CYBLE-224116-01 and CYBLE-224110-00. I have an iOS app I need to update to make FW upgrades to these units and it needs to be able to determine which part is being targeted.
My first round of research hasn't turned up how to retrieve a hardware version string from the unit. I suspect that it is stored as a default characteristic on FW images generated by PSOC creator...but I'm still very new. What's an easy what to do this?Show Less
I changed the device to the new chip, CY8C4125PVS-482:
I was previously using CY8C4245PVI-482. Then, I built the project. Errors resulted.
The first error to fix is the clock speed 48→24 MHz (see imo.png).
The remaining errors are:
What does "fit" and "mpr" mean? Is there reference documentation explaining these errors? I never heard of a macrocell before. Is there a generic solution to these errors?
I recently looking into the 4700S series, but i found that there are not much code example for this series, only 8 of them.
I tried to follow those examples from PSoC4 such as 4200 series etc. but they are significantly different now.
Is there any resources you can share?
The way Cypress update or extend your component library is quite hard to do the sustaining process. All the functions and components are part specific, which is not quite user friendly, just my opinion.
Anyway, please see if you can share any helpful tips. Thanks!
Since PSoC Creator still requires Windows, I've been trying to get it to run on a Windows 11 on ARM64 installation. I've tried a variety of systems, but I think the problem is that I need native ARM64 drivers for the KitProg2 device. Are they available?Show Less
Hello Infineon community!
I finally received my CY8CKIT-059 PSOC5LP. I am a total beginner working with it but I'm looking forward to doing my project with it.
Accelerometer 832M1-0500: Supply: 3.3V Sensitivity@80Hz(mV/g) (X-Y-Z): 3.081-2.534-2.7 Bias Voltage(X-Y-Z): 1.636 1.628 1.659
I'm willing to use the SAR ADC with 12-bit resolution to sample the analog output (60KSPS/channel) of the 3 axes of the Accelerometer. Before the input, I have to filter the signal before with -30dB attenuation at half the sampling frequency.
Can I achieve simultaneous sampling for the 3 axes with the S/H? If not I have to have a minimum sampling of 180KSPS and divide it into 3 to achieve 60KSPS.
Then, I need to transfer the data of the Accelerometer to an ESP32 with SPI then transmit it wirelessly (UDP) (I think this will be another topic)
So I have multiple beginner questions. (I think I will receive some replies that I need to read the datasheet😅)
1) Can I use a power bank to power the PSOC using 5V USB? What about the Vref of the ADC (VDDA VSSA etc.) can they be powered internally? If my application is to be battery powered, do you advise me to use a battery instead of the USB powering?
2) Which ADC SAR inputs (pins) do you advise me to use? Can I use the kitprog's and work only with it? Or do I have to involve the target?
3) I have no idea about how can I filter internally the input. Can you give me some insights?
4) In the screenshot, I need to check if I forgot something, and ask you what should I put as configuration for the ADC if I power the MCU with USB. Vssa to Vdda?
The SPI connection and filtering are my next steps, just when I'm sure I'm on the right track
I am sorry for the beginner questions but I'm still learning so I rushed to post a thread to receive advice from experienced people in the field. Feel free to reply even if just to tell me go work on your datasheets or other constructive remarks😂
Thank you, People!
If I have a firmware that works for the PMG1-S1, will it also work for the more capable PMG1-S2?
If yes, what's the best way to port the firmware code from S1 to the S2?
Lastly, is it possible to load the firmware into PMG1-S1/S2 via the CC interface (like the CCG3PA)? I couldn't find more info from the PMG1 datasheet besides the SWD interface.
What is the procedure of restoring the memory to the factory state when SPI Status Register 1 = 0x41
This can be done through the SafeBoot recovery option.
I want to set the default value of SR / CR
Attached is part of the report from Infineon.
I would like to use the JTAG interface to fix this problem.
#DEFINE ERASE WD=0x06 CE_HI WD=0xDC ADDR_CYCLE4=SA ADDR_CYCLE3=SA ADDR_CYCLE2=SA ADDR_CYCLE1=SA CE_HI WD=0x05 read_status=0bX00XXXX0 CE_HI
#PROGRAM WD=0x06 CE_HI WD=0x12 ADDR_CYCLE4=PA ADDR_CYCLE3=PA ADDR_CYCLE2=PA ADDR_CYCLE1=PA PAGE_SIZE*WD=pd CE_HI WD=0x05 read_status=0bX00XXXX0 CE_HI
#DEFINE PROGRAM WD=0x06 CE_HI WD=0x12 ADDR_CYCLE4=PA ADDR_CYCLE3=PA ADDR_CYCLE2=PA ADDR_CYCLE1=PA WD=pd CE_HI WD=0x05 read_status=0bX00XXXX0 CE_HI
#DEFINE UNLOCK WD=0x06 CE_HI WD=0x01 WD=0x00 CE_HI WD=0x05 read_status=0b00000000 CE_HI
#DEFINE LOCK WD=0x06 CE_HI WD=0x01 WD=0x1C CE_HI WD=0x05 read_status=0b00011100 CE_HI
#READ_PAGE WD=0x13 ADDR_CYCLE4=PA ADDR_CYCLE3=PA ADDR_CYCLE2=PA ADDR_CYCLE1=PA PAGE_SIZE*RD=pd CE_HI
#DEFINE READ_ID WD=0x9F RD=MAN_ID RD=DEV_ID CE_HI
#PROGRAM_TIME 340 750
Hello! I'm using the CYBT-343026-01 module and I've been having problems with the packetization modes of CYSPP. (I'm sending messages via BT and recieving it on PUART)
I was using the deafult anticipated mode but It was sending corrupted messages with a baud rate of 9600. So i decided to change to Immediate mode and it worked perfectly. My problem is that sometimes the module doesn't "remember" it's in immediate mode and works in anticipated mode aparently (It's sending corrupted messages).
When this happens I send a .CYSPPGK command to get the packetization mode, and it indicates its on immediate mode despite it's not working that way.
13:48:55.836 -> .CYSPPGK
13:48:55.836 -> @R,0022,.CYSPPGK,0000,M=00,W=0A,L=14,E=0D
How can I make the module to always work correctly? Is there some parameter I'm missing to configure?