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・IRSM005-301MH
https://www.infineon.com/dgdl/Infineon-IRSM005-301MH-DS-v01_00-EN.pdf?fileId=5546d462533600a40153567bbfdf2860

(p3)
１．Static Electrical Characteristics Driver FunctionのIo＋とIoーは
　それぞれどういう状況でのショート電流を定義しているのでしょうか？
　・VO=0V、VIN=Logic”1”→HINとLINを両方1(ON)にしたときにFETに流れる短絡電流？
　・VO=15V、VIN=Logic”0”→HINとLINが両方0(OFF)のときの短絡電流とはそもそも何でしょうか？　

２．上記１のショート電流は、10μs以内であれば実際に流れても故障に至らないでしょうか？

３．内部のFETに関して、下記のような単品MOSFETにて規定されているような特性図はないでしょうか？
　・VDS(ドレインーソース電圧)　vs　ID(ドレインーソース電流)
　・VGS(ゲートーソース電圧)　vs　ID(ドレインーソース電流)
　・Tj(ジャンクション温度)　vs　RDS(オン抵抗)
　・Safe Operating Area
　・過渡熱インピーダンス

＜補足＞
また、３に関して、IPMはMOSFETとGateDriverが一体型であるため以下URLのシミュレータにて損失確認して使うことが前提とされていると思うのですが、今回の「IRSM005-301MH」はHalf Bridgeでシミュレータ上でも型番が見つかりませんでした。
https://www.infineon.com/cms/en/tools/landing/ipm.html

Dear Sirs and Madams,

We are considering I2S with ModusToolbox.

I know there is a description of "Transmit Streaming" in HAL.

However, we would like to implement this functionality in the PDL rather than the HAL.

Is it possible to provide this "Transmit Streaming" function in PDL description?

Regards,

Dear Sirs and Madams,

We are considering EmEEPROM for PSoC4S MAX.

We would like to confirm the operation when PSoC4S MAX is powered off while the EmEEPROM_Write command is being executed.

I understand that the EmEEPROM_Write command does row writes.

If the power is turned off during row writing, I know that the data in the row being written will not be a normal value,
Is there any possibility of destroying data in other flash areas?

I don't think the bootloader area will be destroyed if the power is turned off while the bootloader application is being written.

Since the PSoC4S series has additional power-on and power-off slew rates, is it okay to negate the XRES pin of PSoC4S MAX as a countermeasure?

Regards,

Hello there,

in multiple papers, it is stated that the classical bridgeless pfc boost converter has bad EMI and the output is floating during negative half-wave.

"[...] in the Dual Boost PFC, the output ground is connected to the ac source only during positive half-line cycle through the body diode of switches. So large pulse current from high frequency switches will flow through parasitic capacitors and brings EMI problems." (Conduction Losses and Common Mode EMI Analysis on Bridgeless Power Factor Correction; Li, Qingnan and Andersen and Michael Andreas E. and Thomsen, Ole Cornelius)

Shouldn't the output ground be connected to the ac source during the negative half-line cycle through the Body-Diode as well?

Best regards

Hello.

I would like to translate the following KBA into Japanese.

https://community.infineon.com/t5/Knowledge-Base-Articles/TRAVEO-T2G-Guidelines-for-exposed-pad-KBA236264/ta-p/372407

Please give permission.

Best Regards,

AkiTmt3

Hello

Regarding CYPD3171 (CCG3PA), if 3.3V is generated from VBUS_IN_DISCHARGE through the internal regulator, please tell me the voltage values for each of the following.

・Min value

・Typ value

・ Max value

Best Regrads

We are trying to configure the CYPD3120 for a display port sink/UFP application with sink pin assignment C (and DP source device pin assignment not supported) We are using the EZ-PD configuration tool but it looks like FW may be over writing the tool setting for SVID 0 bits 15:8 which set the source device pin assignment.  The CYPD3120 always seems to change this field from 0x00 (not supported) to 0x10 (pin assignment E).  Can the device be set for this type of application via the EZ-PD tool or is a FW change required?