I am using  xmc1300 development board for PFC stage in 3.4kW onboard EV charger. In the software for PI  voltage control loop I have to set the max power limit as 3.4kw. This power limit is also used in duty cycle calculation for MOSFET gate signal. The max dc bus voltage at LLC stage is 64v and the  max current rating is 53A.  How to scale this 3.4kW power limit , so that I can use it in the software calculations. I am using DAVE 4.4.2 VERSION.

It is connecting HS device as Upstream. And it is necessary to confirm the HS Host in the USB signal quality test(e.g. Proper Eye Measurement) . Is it necessary to make any settings on the HX2LP for signal quality?
Is there anything else I should do other than putting the Host in test packet mode?

The HX2VL has a TEST pin. Not in HX2LP.

Thanks,
Tetsuo

Here is a system sample program hello_world. The sram usage rate of the program after the default compilation is too high, I now want to reduce the sram usage volume. I have tried to delete some unused libraries in the library manager, but it seems to have no effect. May I ask this How to solve it

• Hardware

  • host: tinker board 2s(rk3399)，kernel 5.13

  • slave: sg130gs(1280*720, YUYV, 30fps) + fpga(spartan 6) + cyusb3014, isochronous mode

• Problem

  • Run this script on host

    #!/bin/bash
    ​
    while : 
    do
            yavta -c30 /dev/video0
            sleep 2
            yavta -c30 /dev/video1
            sleep 2
    done

  • After random time(from minutes to hours), one of these cameras would be stuck

  • USB packets captured by tcpdump indicate that the host keeps polling(isochronous) the slave while the slave keeps responding with a data packet with zero-length

  • After this, if I restart the test script, the device that is stuck will be missed

• some trials on other settings also failed

  • ov5640(1280*720, YUYV,30fps) + cyusb3014, bulk mode

  • sg130gs(1280*720, YUYV, 30fps) + fpga(spartan 6) + cyusb3014, bulk mode

• In addition, test with a single camera is fine

Any ideas? thanks

To whom it may concerned ,

a CCG2 is emplyed on our USB4 Gen3 cable product which undergoes the compliance test w/ 3 items failed — 

1)Ra is out of 800 Ohm ~ 1.2K Ohm ( 3 pcs  tested and 1/3 ok w/ Vconn @423 mV ,and 2 out of 3 NG w/ Vconn = 402 mV )

2) PD3 modes - checking SVIDs ( The UUT shall return a number of SVIDs in between 1 and 1, actual 2 (TEST.PD.VDM.CBL.1#3)

3)Checking Headers (Message ID 0): Manufacturer String shall be null terminated (COMMON.CHECK.PD.10#1 x 1)

Kindly advise the countermeasure of the above 3 issues.

f.y.i. 1）NG test report 2）SVID on VIF 3）SVIDs setting on CCG2 are on the attached photos。

Thank you and best Regards,

Alan Huang 

From the photo above, are we able to identify the part is genuine and originated from Cypress factory?

The country origin is different, I would hope to find out if the parts at the left side is genuine as X-ray photo shown the die paddle is different from my past receipt 

Hi.

I have a dual-cpu design, based on one of the Cypress/Infineon example projects and document AN215656. I now need to implement DFU, but all the available examples assume a single CPU design. Since both dual-CPU and DFU are largely based on linker-script magic, this makes for a difficult situation.

Is there any additional guidance - example projects or documentation - on how to go about this? Or has anyone had experience doing this? All help will be greatly appreciated, as I'm not looking forward to navigating this minefield on my own.

Thanks,

-Nick

I am creating a project to utilize the ADC of the PSoC6 as a thermistor circuit and the CapSense separately. When I try to generate the application I get analog pin errors. Can the PSoC6 only support either the ADC or CapSense at once? And if so does anyone have a recommendation on easy to interface external ADC's?