I'm using the Counter component (UDB - 32-bits). I'm using this component to measure time.
So, when I'm doing step-by-step debugging, I'd like it to paused.
What I noticed is that the Counter keeps updating even if the program is paused while I'm debugging it.
Is it possible to do that? Perhaps it is a simple as pausing the Clock that drives it... but how to do that? Thanks!Show Less
We are using the PSOC 6 - CY8C63x7 Architecture.
We found on it's technical reference manual an possible option to switch on and off the JTAG(DAP) connection.
It can be found on page 136 -
"The second bit, CPUSS_AP_CTL.xxx_ENABLE, is a regular
read/write bit. This bit also resets to zero and is set to ‘1’ by
either the ROM boot code or the flash boot code depending
on the life-cycle stage. This feature can be used to block
debug access during normal operation, but re-enable some
debug access after a successful authentication"
1. Is this feature really possible?
2. Is it enabled/disabled only from the bootloader?
3. Is there an option to enable/disable JTAG connection from the user application space?
Appreciate your help!
I have two questions:
1. Where can I find out timings for reading and writing to ports and registers including DMA transfers? I have a time-critical application and want to know the numbers.
I ran a simple test to see how fast I could write to a pin using API write function, direct write to the port address, bit-banding; then writing to a control register connected to a pin. The results were surprising in that the bit-banding took more clock cycles than a direct write; also, the number of clock cycles jumped at 48MHz, from typically 6 to 14.
Clearly, this isn't a simple issue.
2. Regarding warnings about asynchronous paths: if I get a warning about an asynchronous input that is used as a clock on a D-type, this means that the D-type is actually clocked on the internal clock edge, not my external clock. Otherwise it wouldn't matter, no? If I use a Sync component, I'll lose another clock cycle: one to get through the Sync and the next to clock the D?
I think the Sync component is basically a D flip-flop anyway so, despite the warning, I get no benefit from using it and delay my signal unnecessarily.
Am I wrong here?Show Less
Hi guys! I am new in the cypress community, I hope that you can help me with this issue. I am trying to read an encoder without using interrupts. The solution that came to my mind is to use a counter in UpCnt & DwnCnt mode. I have tried almost everything but the function Counter_ReadCounter(); returns me always the period value. I cannot understand how to fix it. Pin_encoder_B and Pin_encoder_A are my two signal wires that go high and down. I am using Pin_encoder_A as a clock, when it turns up I look at the Pin_encoder_B, if Pin_encoder_B and Pin_encoder_A are equal or disequal I understand if my encoder is tourning clockwise or counterclockwise and I should be able to decrement or increment my counter. What is wrong in my code? Thank you all.
I have imported a project that was written for another kit. I changed the target= in the makefile and changed the
Library Manager to my kit which is CY8CKIT-062S2-43012
it was CY8CPROTO-062-4343W
I try to build and I get 6 Errors as follows:
Description Resource Path Location Type
#error "MBEDTLS_PSA_ITS_FILE_C defined, but not all prerequisites" check_config.h /mtb_shared_2/mbedtls/mbedtls-2.22.0/include/mbedtls line 580 C/C++ Problem
make: *** [../mtb_shared/core-make/release-v1.9.0/make/core/main.mk:434: secondstage_build] Error 2 Nanodrone_II C/C++ Problem
make: *** [../mtb_shared/core-make/release-v1.9.0/make/core/build.mk:387: C:/PSoC6/Nanodrone-II_PSoC6-main/build/CY8CKIT-062S2-43012/Custom/ext/mtb_shared/mbedtls/mbedtls-2.22.0/library/aes.o] Error 1 Nanodrone_II C/C++ Problem
make: *** [../mtb_shared/core-make/release-v1.9.0/make/core/build.mk:387: C:/PSoC6/Nanodrone-II_PSoC6-main/build/CY8CKIT-062S2-43012/Custom/ext/mtb_shared/mbedtls/mbedtls-2.22.0/library/aesni.o] Error 1 Nanodrone_II C/C++ Problem
make: *** [../mtb_shared/core-make/release-v1.9.0/make/core/build.mk:387: C:/PSoC6/Nanodrone-II_PSoC6-main/build/CY8CKIT-062S2-43012/Custom/ext/mtb_shared/mbedtls/mbedtls-2.22.0/library/arc4.o] Error 1 Nanodrone_II C/C++ Problem
make: *** Waiting for unfinished jobs.... Nanodrone_II C/C++ Problem
not sure what the errors mean?
can anyone point me in the right direction so I can build this project.
makefile is attached
Steve KShow Less
I am planning on taking a course on embedded sensors on Coursera which uses the CY8CKIT-059. However, I am unable to find this kit in stock anywhere online. I was wondering if the CY8CKIT-050 kit could be used instead. I do not have much electrical or development kit background.
We used the CYPD4226-40LQXIT before on another project that for USB-C PD with 100W max and it is working fine. For this new design I tried to use the same PD circuit to two USB-C ports but due to the input power limitation we could only have one USB-C port with full PD function (100W max) and another USB-C port with 5V @ 1.5A output only. Can the CYPD4226-40LQXIT can program to output only 5V @ 1.5A max even the connected target device support full range?
How can I replace an HX2VL, CY7C65632-28LTXC, with a HX3, CYUSB2304-68LTXI?
Is it possible to set PID or Maximum Power in ROM on HX3?
Configuration of the HX2VL is default, no EEPROM, which appears to match some defaults of HX3, but not all. VID and Port defaults appear to be the same. PID for HX2VL = 6570h and for HX3 = 6503h. I don't see Maximum Power report option in HX3. Maximum Power default is 100 (32h) in HX2VL.
Any help, words of wisdom or lessons learned on the effort to change from HX2VL to HX3 would be appreciated.
I'd prefer to NOT add a configuration EEPROM.
I've created a relatively simple sinewave generator for audio testing applications. It uses a CY8CKIT-059 but can be easily adapted to other PSoCs that have a WaveDAC8 component.
The project supports the following audio frequencies (in Hz):
I'm using the USB IMO clocking which is suppose to be +/- 0.25% accuracy.
I've used this device to test some audio equipment for frequency response such as tri-powered speakers and mixers with equalization features.
It also has the following features:
You can use fixed resistors to limit the drive the segments of the 7-segment display. I chose to use the SIO outputs (Port 12) with voltage regulation. I used a 30 ohm resistor on the common line of the segments. I then monitor the voltage across this resistor. The voltage represents the combined current flowing through the segments being turned on.
The target current per segment in this design is 4mA. There for the digit '8', all 7 segments are lit and should have a combined current of 7 x 4mA = 28mA (= 0.840V / 30 ohms). Therefore I can increase the voltage of VDAC8_LED_vref until I get 0.840V across this resistor. For the digit '1' (2 segments), I target 2 x 4mA = 8mA => 8mA * 30 = 0.240V.
Why did I do this? Besides reducing external components (8 resistors to 1 resistor), because I could! This technique has its limitations but is useful as a learning exercise.
You can use this to learn how to use the SIO port pins in a voltage regulation mode as well as using the ADC to create a feedback control loop.
Here are a couple of pics of the assembled project:
To the Moderator:
Can you delete spam message from discussion thread:
unable to get real time capsense tuner functioning... - Infineon Developer Community
It's the message posted by visitor serpodrik, Oct 26, 2021 05:55 AM.