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Could I expect some sort of response from your side? Like previous regarding repeated scans? It's a humble request.

Traceback (most recent call last):
  File "C:\Users\Avinash\Music\Potentiostat_SW_A9\Potentiostat_communication.py", line 80, in usb_read
    usb_input = self.ep_in.read(size, timeout)
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\core.py", line 301, in read
    return self.device.read(self.bEndpointAddress, size, self.interface, timeout)
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\core.py", line 656, in read
    return fn(
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\backend\libusb0.py", line 481, in bulk_read
    return self.__read(_lib.usb_bulk_read,
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\backend\libusb0.py", line 566, in __read
    ret = int(_check(fn(
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\backend\libusb0.py", line 387, in _check
    raise USBError(errmsg, ret)
usb.core.USBError: [Errno None] b'libusb0-dll:err [_usb_reap_async] timeout error\n'

Traceback (most recent call last):
  File "C:\Users\Avinash\Music\Potentiostat_SW_A9\Potentiostat_communication.py", line 80, in usb_read
    usb_input = self.ep_in.read(size, timeout)
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\core.py", line 301, in read
    return self.device.read(self.bEndpointAddress, size, self.interface, timeout)
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\core.py", line 656, in read
    return fn(
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\backend\libusb0.py", line 481, in bulk_read
    return self.__read(_lib.usb_bulk_read,
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\backend\libusb0.py", line 566, in __read
    ret = int(_check(fn(
  File "C:\Users\Avinash\AppData\Local\Programs\Python\Python310\lib\site-packages\usb\backend\libusb0.py", line 387, in _check
    raise USBError(errmsg, ret)
usb.core.USBError: [Errno None] b'libusb0-dll:err [_usb_reap_async] timeout error\n'

Code----

IPB720P15LMのシミュレーションモデルございますでしょうか？

Webで確認した所、モデルがございませんでしたので、ご確認頂ければと思います。

【製品URL】

https://www.infineon.com/cms/en/product/power/mosfet/p-channel/ipb720p15lm/#!order

以上、宜しくお願い致します。

Dear supporter

I want to translate the following KBA(KBA236254), please confirm to my work.

https://community.infineon.com/t5/Knowledge-Base-Articles/Does-Infineon-specify-TJ-and-%C6%9FJA-values-for-flash-devices-KBA236254/ta-p/373325

Best Regards.

YuMa

I'm using P2G kit to develop a UART communication. I use FIFO buffer to transmit and receive UART Interrupt mode. 

Ex: 

UART_Receive(&UART_0, uart_instance.payloadISR, sizeof(uart_instance.payloadISR)); (payload is 5 bytes length). FIFO buffer 16 bytes.
I see in the comment of UART_Receive that FIFO buffer will be flushed after I receive full of my desire bytes (here is 5 bytes). But in practice I see that buffer is not flushed as expectec.
For example, I receive 5 bytes, communication is successful as expected. But when I receive 4 bytes, and next time sender send another msg with 5 bytes, 1 byte in the 2nd msg will be fill in the missing one in the 1st msg. Yeah it's ok at this part. But I expect that other 4 bytes remain in 2nd msg will be flushed, so when the 3rd msg with full 5 bytes arrive, it will not occur the situation like the 1st and 2nd msg. But I see that 3rd is still suffer that problem, and other msg continue the same, until the nth msg, everything is ok, 5 bytes receive correctly again (I do not know when the nth msg arrive, sometime it 4th, 8th,... it's not stable). Hope to hear the answer from you guys. Thanks.

Hi,

This is an inquiry with Audio_sink in the sample code.

I have "ENABLE_EBUG?=1" as below, but it doesn't recognize ENABLE_DEBUG as 1.
I do a make clean and make ENABLE_DEBUG=1 program. but it has no effect.

How do I get ENABLE_DEBUG to be 1?

Best regard,Yuki

Hi everyone
Good day~

I don't know the differences between TLE5028C-XAI & TLE5028C-XAA from the datasheet.

The following is my opinion, I don't know if it is correct:
TLE5028C-XAI-D28         CW 90us, CCW 45us
TLE5028C-XAA-D28       CW 45us, CCW 90us

Or is there a better description different from the datasheet?

Best Regards
Rsiigod

Planning to use TPM 2.0 in an upcoming application and was wondering if there's a way to zeroize the TPM module? In other words, wipe any keys or information on the TPM module. I have not been able to find any information on this.

Thanks.

In PSoC4000S Device-Family there are devices with 48MHz and 24MHz max. CPU speed. The term 'CPU speed' is used in PSoC4000S data sheet and it's not exactly clear to me what this means.

For PSoC4000S devices with max. CPU speed of 24MHz,  which clock is limited to 24MHz?

1. Clock frequency of IMO is max. 24MHz
2. Clock frequency of HFCLK is max. 24 MHz
3. Clock frequency of SYSCLK is max. 24 MHz

If the term 'CPU speed' corresponds to SYSCLK frequency, is it possible to use higher clock frequencies for IMO and HFCLK? For example IMO = 48MHz , HFCLK = 48MHz, SYSCLK = 24MHz

Does the max. CPU speed only restrict CPU core clock or peripheral clocks as well?