I am having one more problem with FX2LP while streaming video data.
Please help us to understand if while requesting data from FX2LP is there a possibility of FX2LP endpoint buffer getting stuck? Means FLAGB activity stops and no further data exchange happens.
When I was testing on EVK with the bulksrc example I found that if the EP buffer is not full and you request data from it then it will get stuck. Can the same scenario happen in webcam stream mode also? If so, then what are all the conditions in which we can get into this state? Please help to understand this.
Hello all, I am working on FX3 while interfacing a camera sensor with it. I need to debug and as mentioned that there are some ways to do so using segger debugger. I want to connect it on board. What pins I need to use to connect the segger JTAG (2*10 pins connector).
Dear Sirs and Madams,
Please tell us about the contents described in the application note AN85951.
Section 7.4.2 contains the following :
"You should use flex circuits with thickness 0.01 inches (0.25 mm) or higher for CapSense."
What does the 0.01 inch shown in this sentence mean?
Is it the thickness of the flexible substrate?
Or is it the thickness of the copper foil on the flexible substrate?
We would like to know what 0.01 inch refers to.
I have essentially the same question that was addressed in this post: CY7C65631 linux compatiblity and few questions.
It has a disposition of solved, but I am not finding the answer in the link to the solution. The message board would not let me reply directly to that post, so I am re-posting here.
Specifically, I need to know how to perform the in-circuit programming of the EEPROM on an embedded linux target. I have the CY7C65631 device designed in, with the recommended 25LC040T/SN EEPROM, and I am working now to figure out how to get it programmed.
Here is the response from Sananya:
HX2LP can work on a Linux host since it needs standard hub class drivers which are present with Linux.
The EEPROM doesnt have to be pre-programmed as HX2LP is capable of programming the EEPROM using Blaster utility. You could also eliminate the EEPROM since it has a ROM with default configuration that it can use for boot-up. However, please ensure that the SPI data line has the required pull-down resistor even when not connected. Please refer to 25LC040 which is used in the HX2LP CY4606 DVK.
Yes, an oscillator can also be used instead of the crystal. You can refer to the App Note for clock requirements-https://www.cypress.com/documentation/application-notes-obsolete/an49150-schematic-and-layout-review-checkli...
I'm using CYBT-353027 bluetooth module.
Please teach me about the failure mode of this module.
What is the failure mode when an overvoltage is applied to the VDDIN?
In particular, what happens if 4.3 volt is applied to the VDDIN pin?
I am using ModusToolbox build system in the IDE mode.
Is there a way in the Makefile to make the CFLAGS to be applied only to user (my) source code files, and not to all the framework source files ?
Is it possible for an application to overwrite the factory value of CY_SFLASH_USBMODE_IMO_GAIN_TRIM_REG or other registers in SFLASH, so the PSoC will reboot with the new values stored in SFLASH?
I know that the value of CY_SYS_CLK_IMO_TRIM4_REG can be modified at runtime. However, I have a situation where the PSoC could be updated by a customer to older, existing software. That is why I need to modify the trim value permanently.
Is there maybe some special mode using the MiniProg3 and PSoC Programmer, to write SFLASH registers?
I would like to check about the CTS/RTS Pin condition of the HCI UART port of CYBT-343026-01.
The following library states that the CTS pin must be at a high level at reset in order to enter HCI mode.
>(2) Pull the CTS to high during power on reset or hardware reset.)
Is there any specification for RTS?
Also, what is the HW pin configuration of the CTS and RTS pins during reset? (e.g. Input Pullup).
The next question is about the CTS/RTS pin condition when using UART in RAW mode. Are the conditions same to HCI mode or different?
The last question, can I use the HCI UART without flow control (without CTS/RTS) if I adjust the pin conditions of CTS/RTS to the initial conditions of the above question?
We are looking on using a EtherCAT ESC chip (LAN9252) together with a PSoC5LP.
The LAN9252 chip can be connected over a host bus interface (chapter 9 of the datasheet).
I would prefer to connect it to the PSoC in multiplexed mode in which 16 lines are used for the address and data, with a single line to latch the address.
I have looked into hooking this up in the PSoC5LP and found the External Memory Interface (EMIF).
However, looking at that component I saw no configuration to multiplex the address and data lines.
Is there any standard component that could provide multiplexed address/data lines towards the LAN9252 chip?
It might be possible to create a circuit (inside or outside PSoC) to perform the latching, but I would rather not go that route.
Any thoughts?Show Less
Please correct me or give me some advise about how to test and use the wake on wireless lan function.
I suppose the released driver is capable of assert WL_HOST_WAKE when receive magic packet and do the following steps.
iw phy0 wowlan enable disconnect magic-packet
echo "standby" > /sys/power/stat