Hello everyone,

I have an app that we wrote using an older version of the CyUSB library that I'm moving to the modern version in an effort to support a newer board that uses the FX3 instead of the SX2. One of the things the app does is when it's cleaning things up at the end is call the abort function to cancel any ongoing communications. 

I've found that when we call that function now though, the function never returns, which locks up the app.

Do you have any idea why this might be happening, or what I could do to investigate further? Is there a trick that I should know about working with this object beyond what I've read in the programmer's reference?

Dear all,

I already own a CYW20706B2 Evaluation KIT. I want to connect it to an Audio codec and use the share-clock feature on CYW20706(GPIO BT_CLK_REQ/P4/P24) as MCLK (Master clock) for driving the Audio codec.

As i know, the default state of this GPIO is BT_CLK_REQ enabled, with double checking i can make sure that no more configurations for this GPIO in my project. However, when i connect the Logic Analyzer to pin 3 (J19) or pin 5 (J21) to visualize the output clock then nothing happen, there is no clock pulse. 

I would really appreciate if anyone could give me a hand on how to reconfigure this Share-clock feature.

Hello,

I am working with PSoC-4 and want to know what is the PSoC-4 boot time. How much time it take for executing the first line of main() upon power-up. I could not find this data from Cypress website. 

Please help.

Thanks,

Kurian Polachan

We'd like to implement a solution based on CYBT-353027-02 module (CYW20706) that has both HFP and HF Audio Gateway functionality. That means, our product shall be able to connect to a mobile phone and a headset simultaneously and forward eSCO audio between those 2 devices and the host CPU connected to it via its PCM interface.

                  |---------------------------------|
     Headset <--> | AG            |                 |
                  |   CYW20706  |PCM| <-> Host CPU  |
Mobile Phone <--> | HF            |                 |
                  |---------------------------------|

So, I have the following questions:

1. Is described above possible at all?
2. Is CYW20706 able to support 2 (e)SCO connections simultaneously?
3. How audio routing between those 2 (e)SCO connections is done?
4. Can we route audio between PCM interface and 2 (e)SCO connections on-the-fly? How?
5. How CYW20706 mixes audio with different codecs, say, if one audio stream is mSBC-encoded and another one uses CVSD?
6. Actually, we can mix the audio at host side. Is it possible to use 2 stereo channels at PCM interface to, for example, forward HF audio to the left channel and AG audio to the right channel? How to do that?

Processor card: KIT_XMC4400_DC_V1 

Drive board:   EVAL-M5-IMZ120R-SIC  board.   

Question:  How to set absolute current limit in software for I-V, I-U and I-W?   

Problem:  we can drive the motor for 2s.  However, the current of I-V/U/W keep increasing.  then trigger the CTRAP ..  

Thanks 

Hello team,

I am using the demo example from https://github.com/Infineon/AURIX_code_examples/tree/master/code_examples here. In MBIST demo example, default MBIST is for DMA. By using ADS compiler, MBIST test is passing correctly. But if used same example for testing the CPU0_DSPR(test_MTU_MBIST(IfxMtu_MbistSel_cpu0Dspr);), it is failing in the highlighted instruction i.e. while enabling the SSH for CPU0. Please let me know the reason befi

Please help me to perform MBIST for different IP in TC387. 

Hey Sir,

MCU CY8C6347BZI-BLD54 is used as a CPU on our product and it has been produced for 50K-100K units. However, there are a few units (less than 1%) having boot-up issue after executing the process of secure boot. The failure symptoms are listed below:

1. Power up for several cycles and then finally it could boot up successfully. The cycle time of powering up can't be calculated. It's a random.

2.  Always fail to boot up so it becomes a brick.

3.  1 unit succeeds to boot up intermittently.

The eFuse of these units is burned successfully if we check the eFuse bit after the unit succeed to boot up. Thus, we can't read any debug information from the SWD port. Then some signal waveforms are captured and compared on both the situation of successful and fail boot-up. The main differences are

1. The power rail behavior of MCU_VIND2, MCU_VRF, and MCU_VBUCK1

2. The activated timing of SWDIO

Please refer to the attachment for more detail waveforms. We suspect this issue results from the process of eFuse burning but we don't have solid evidence to prove it. Thus, we need your thoughts and insights on this issue. It's getting more critical now due to the increasing production volume. Thanks.

Hello! I'm using the CYBT-343026-01 module and I've been having problems with the  packetization modes of CYSPP. (I'm sending messages via BT and recieving it on PUART) 

I was using the deafult anticipated mode but It was sending corrupted messages with a baud rate of 9600. So i decided to change to Immediate mode and it worked perfectly. My problem is that sometimes the module doesn't "remember" it's in immediate mode and works in anticipated mode aparently (It's sending corrupted messages). 

When this happens I send a  .CYSPPGK command to get the packetization mode, and it indicates its on immediate mode despite it's not working that way. 

UART Commands:

 13:48:55.836 -> .CYSPPGK
13:48:55.836 -> @R,0022,.CYSPPGK,0000,M=00,W=0A,L=14,E=0D 

How can I  make the module to always work correctly? Is there some parameter I'm missing to configure?

I am working with CY8CKIT-059 and need help discerning the differences between my custom project and one of the projects provided under "Find code example..." dialogue. 

I have a device that is acting as an I2C Master and is connected to the CY8CKIT-059 acting as an I2C slave. 

If I use the sample project: "DelSig_I2CS" I can  successfully perform a Write operation from the external device and the CY8CKIT-059 running the sample project can successfully ACK the address and receive the 2 bytes being written to it.  No issues here, I2C slave is working as expected. 

However when I generate a new project, and reuse the code from the sample I2C project and set up the I2C peripheral in the same way the sample project has it configured, the CY8CKIT-059 NACKs the address and no data is received. 

Perhaps I am not setting up the custom project in the same way, but I think I have checked everything. 

What are some probable causes as to why the CY8CKIT-059 would NACK when being addressed?

I will attach both projects: DelSig_I2CS is working just fine with no issues and "Roadrunner2_Eval which I believe is setup in the same way. 

In general, both projects have the same code:

At this point Delays are being used to have a line of code to attach breakpoints to. 

I2CS_Start();

/* Set up slave read data buffer */
I2CS_SlaveInitReadBuf((uint8 *) sample_segment, RD_BUFFER_SIZE);
I2CS_SlaveInitWriteBuf((uint8 *) sample_segment, RD_BUFFER_SIZE);

/* Enable global interrupts - needed for I2C operation */
CyGlobalIntEnable;

Enter Main Loop:

/* Check if the slave buffer has been Written */
if(I2CM_SlaveStatus() & I2CM_SSTAT_WR_CMPLT)
{
     byteCount = I2CM_SlaveGetWriteBufSize();
     I2CM_SlaveClearWriteStatus();
     I2CM_SlaveClearWriteBuf();

/* If both bytes of the read buffer have been read */
if(byteCount == I2C_BUFFER_SIZE)
{
     CyDelay(1);
     return 1;
}
else /* Wrong number of bytes read - place error handling code here */
{
     CyDelay(1);
}


/* Check if the slave buffer has been read */
if(I2CM_SlaveStatus() & I2CM_SSTAT_RD_CMPLT)
{
     byteCount = I2CM_SlaveGetReadBufSize();
     I2CM_SlaveClearReadStatus();
     I2CM_SlaveClearReadBuf();

/* If both bytes of the read buffer have been read */
if(byteCount == I2C_BUFFER_SIZE)
{
     CyDelay(1);
     return 1;
}
else /* Wrong number of bytes read - place error handling code here */
{
     CyDelay(1);
}